Patents by Inventor Masatoshi Taya
Masatoshi Taya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11398411Abstract: The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.Type: GrantFiled: June 19, 2020Date of Patent: July 26, 2022Assignee: NEXCHIP SEMICONDUCTOR CO., LTD.Inventors: Masatoshi Taya, Norio Nakano, Yasuhiro Kumagai
-
Publication number: 20210398860Abstract: The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.Type: ApplicationFiled: June 19, 2020Publication date: December 23, 2021Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.Inventors: MASATOSHI TAYA, NORIO NAKANO, YASUHIRO KUMAGAI
-
Publication number: 20210020630Abstract: The present disclosure provides a high-voltage tolerant semiconductor element preventing performance deterioration caused by impurity diffusion. The high-voltage tolerant semiconductor element includes a source portion (S), a well impurity region (PW) disposed around the source portion (S), and at least two gate portions (G) disposed at two sides of the source portion (S). An impurity concentration of the well impurity region is higher than an impurity concentration of a silicon substrate. A space between the two gate portions (G) is greater than a diffusion length (DD) of impurities.Type: ApplicationFiled: June 15, 2020Publication date: January 21, 2021Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.Inventors: MASATOSHI TAYA, NORIO NAKANO, YASUHIRO KUMAGAI
-
Patent number: 10373862Abstract: Provided is a semiconductor device including an active region defined by a separation region on a main surface of a semiconductor substrate, and a field effect transistor formed in the active region. A boundary portion, over which a gate electrode pattern strides, is disposed in a boundary between the active region and the separation region and is configured such that a length of one side, in a direction of a gate length of the field effect transistor formed in the active region, becomes larger than the gate length and does not come into contact with at least one of a pair of source and drain regions of the field effect transistor.Type: GrantFiled: July 27, 2016Date of Patent: August 6, 2019Assignee: Synaptics Japan GKInventor: Masatoshi Taya
-
Publication number: 20170032999Abstract: Provided is a semiconductor device including an active region defined by a separation region on a main surface of a semiconductor substrate, and a field effect transistor formed in the active region. A boundary portion, over which a gate electrode pattern strides, is disposed in a boundary between the active region and the separation region and is configured such that a length of one side, in a direction of a gate length of the field effect transistor formed in the active region, becomes larger than the gate length and does not come into contact with at least one of a pair of source and drain regions of the field effect transistor.Type: ApplicationFiled: July 27, 2016Publication date: February 2, 2017Inventor: Masatoshi TAYA
-
Patent number: 9269707Abstract: In IC chips for display device driving, an operational amplifier is widely used in input and output circuits, and a capacitor in a medium withstanding voltage chip is used as a compensation capacitor. As for this product area, cost competitiveness is very important. Therefore, a MIS capacitor with good area efficiency is widely used. However, unlike a so-called varactor widely used in a VCO circuit, a characteristic of as small a voltage dependence of the capacitor as possible is used. Therefore, an additional process is added to reduce the voltage dependence of the capacitor, but there is a problem of an increase in process cost. A semiconductor substrate side capacitor electrode in a MIS capacitor within a first conduction type medium withstanding voltage chip used in an I/O circuit or the like on a semiconductor integrated circuit device is formed in a first conduction type low withstanding voltage well region.Type: GrantFiled: December 4, 2014Date of Patent: February 23, 2016Assignee: Synaptics Display Devices GKInventors: Masatoshi Taya, Kunihiko Kato
-
Publication number: 20150162323Abstract: In IC chips for display device driving, an operational amplifier is widely used in input and output circuits, and a capacitor in a medium withstanding voltage chip is used as a compensation capacitor. As for this product area, cost competitiveness is very important. Therefore, a MIS capacitor with good area efficiency is widely used. However, unlike a so-called varactor widely used in a VCO circuit, a characteristic of as small a voltage dependence of the capacitor as possible is used. Therefore, an additional process is added to reduce the voltage dependence of the capacitor, but there is a problem of an increase in process cost. A semiconductor substrate side capacitor electrode in a MIS capacitor within a first conduction type medium withstanding voltage chip used in an I/O circuit or the like on a semiconductor integrated circuit device is formed in a first conduction type low withstanding voltage well region.Type: ApplicationFiled: December 4, 2014Publication date: June 11, 2015Inventors: Masatoshi TAYA, Kunihiko KATO
-
Patent number: 8860169Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: GrantFiled: November 6, 2013Date of Patent: October 14, 2014Assignee: Renesas Electronics CorporationInventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
-
Publication number: 20140061847Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: ApplicationFiled: November 6, 2013Publication date: March 6, 2014Applicant: Renesas Electronics CorporationInventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
-
Patent number: 8604583Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: GrantFiled: April 3, 2012Date of Patent: December 10, 2013Assignee: Renesas Electronics CorporationInventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
-
Patent number: 8546905Abstract: To reduce size of a finished product by reducing the number of externally embedded parts, embedding of a Schottky barrier diode relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. It is general practice to densely arrange a number of contact electrodes in a matrix over a Schottky junction region. A sputter etching process to the surface of a silicide layer at the bottom of each contact hole is performed before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.Type: GrantFiled: February 10, 2012Date of Patent: October 1, 2013Assignee: Renesas Electronics CorporationInventors: Kunihiko Kato, Shigeya Toyokawa, Kozo Watanabe, Masatoshi Taya
-
Publication number: 20120326262Abstract: To reduce size of a finished product by reducing the number of externally embedded parts, embedding of a Schottky barrier diode relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. It is general practice to densely arrange a number of contact electrodes in a matrix over a Schottky junction region. A sputter etching process to the surface of a silicide layer at the bottom of each contact hole is performed before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.Type: ApplicationFiled: February 10, 2012Publication date: December 27, 2012Inventors: Kunihiko KATO, Shigeya TOYOKAWA, Kozo WATANABE, Masatoshi TAYA
-
Publication number: 20120187520Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Inventors: Kunihiko KATO, Hideki YASUOKA, Masatoshi TAYA, Masami KOKETSU
-
Patent number: 8222712Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.Type: GrantFiled: March 8, 2009Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Kunihiko Kato, Shigeya Toyokawa, Kozo Watanabe, Masatoshi Taya
-
Patent number: 8169047Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: GrantFiled: September 5, 2008Date of Patent: May 1, 2012Assignee: Renesas Electronics CorporationInventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
-
Patent number: 8067807Abstract: In an LCD driver IC, a high-breakdown-voltage MISFET is mounted together with a typical low-breakdown-voltage MISFET. Because the high-breakdown-voltage MISFET has a gate oxide film thicker than that of the typical MISFET, the electrode of the high-breakdown-voltage MISFET is inevitably high in level. Accordingly, the depth of a gate contact is shallow so that process compatibility with the typical portion is necessary. In the present invention, in, e.g., the channel width direction of the high-breakdown-voltage MISFET, the boundary of a thick-film gate oxide region is located inwardly of the end of a gate electrode. At the gate electrode portion thus lowered in level, a gate contact is disposed so that the boundary of the thick film is located inwardly of the end of the gate electrode and between the gate contact and a channel end.Type: GrantFiled: July 23, 2009Date of Patent: November 29, 2011Assignee: Renesas Electronics CorporationInventor: Masatoshi Taya
-
Patent number: 7777294Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.Type: GrantFiled: October 7, 2005Date of Patent: August 17, 2010Assignee: Renesas Technology Corp.Inventor: Masatoshi Taya
-
Publication number: 20100052073Abstract: In an LCD driver IC, a high-breakdown-voltage MISFET is mounted together with a typical low-breakdown-voltage MISFET. Because the high-breakdown-voltage MISFET has a gate oxide film thicker than that of the typical MISFET, the electrode of the high-breakdown-voltage MISFET is inevitably high in level. Accordingly, the depth of a gate contact is shallow so that process compatibility with the typical portion is necessary. In the present invention, in, e.g., the channel width direction of the high-breakdown-voltage MISFET, the boundary of a thick-film gate oxide region is located inwardly of the end of a gate electrode. At the gate electrode portion thus lowered in level, a gate contact is disposed so that the boundary of the thick film is located inwardly of the end of the gate electrode and between the gate contact and a channel end.Type: ApplicationFiled: July 23, 2009Publication date: March 4, 2010Inventor: Masatoshi TAYA
-
Publication number: 20090243027Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.Type: ApplicationFiled: March 8, 2009Publication date: October 1, 2009Inventors: Kunihiko KATO, Shigeya TOYOKAWA, Kozo WATANABE, Masatoshi TAYA
-
Publication number: 20090065888Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a main surface of a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region in circular form, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: ApplicationFiled: September 5, 2008Publication date: March 12, 2009Inventors: KUNIHIKO KATO, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu