Abstract: A program parallelizing apparatus for generating from a source program to be executed an object program which is capable of being processed in parallel by a plurality of processors constituting a multi-processor which includes a communication mechanism for allowing inter-processor communication and a synchronization mechanism for allowing the processings to proceed in parallel among the processor through coordination. Object programs susceptible to parallel processing by the multi-processor system with high efficiency can be generated at a high speed in correspondence to various source programs universally independent of the types of processors.

Abstract: In place of a controlled object structure, a reaction force simulating actuator is connected to an actuator controlling the structure for recording a displacement at the connecting point. A reaction force at the connecting point after a given period of time is calculated by a digital computer on the basis of the measured value of the displacement and so forth and a known external force. The reaction force simulating actuator is actuated to realize the reaction force calculated value after the given period of time. Accordingly, since a load substantially corresponding to the reaction force from the controlled object structure is provided to a drive device, a test of the controlling drive device to be used in a condition difficult to realize can be performed under substantially similar conditions as in actual usage.

Abstract: A vibration testing system is economical and has high precision in realizing an equivalent test condition for testing for an entire structure, by employing a partial model by coupling testing of a partial structure and analysis of a numerical model with respect to a large structure or a structure having a portion that is difficult to establish the numerical model. In the vibration test using an actuator, a reaction of the member of the structure is detected to derive a vibration response after a given period of time at a boundary between the numerical model and the member. Excitation is performed so that the response of the actuator after the given period becomes consistent with a calculated value to make it possible to apply the response calculated with respect to the numerical model to the member by the actuator at the same timing to the actually occurring timing.

Abstract: A circuit board includes a circuit-conductor layer, a ground layer and a power source layer superposed in a multilayer form through dielectric layers therebetween, A heat conduction through inside of the circuit board is enhanced so that circuit chips mounted on the circuit board can be cooled down to a level capable of operating normally, The circuit board can be formed to be compact, In order to enhance the heat transfer in the circuit board, at least one of the ground layer and power source layer is formed in a multilayer manner, It is preferable to form these layers at a thickness larger than that of the circuit-conductor layer, Further, preferably, the pin of the chip mounted on the board and at least one of the ground layer and power supply layer are connected to each other in such a manner as to enhance the heat conduction.

Abstract: A controller (MSC) for generating a basic control signal to permit a CPU to access to a resource in a processor system is arranged in each of local control blocks. The MSC is operated not by a basic clock supplied to the CPU but by a clock which is generated prior to the clock supplied to the CPU and which passes through the MSC and is precisely controlled for delay. Thus, the delay of a control signal to be supplied to the CPU relative to the reference clock is minimized and a high speed operation of the system is attained.

Abstract: When a plurality of processors share a plurality of tasks and parallelly process the shared tasks, each of these processors outputs bit information for designating a processor in a group to which the processor belongs, when a currently executed task processing has been terminated, and the bit information is stored in a synchronous register disposed in each of the processors. When it is detected that all of processors in the same group have terminated task processings, each of these processors in the same group are supplied with a synchronization termination signal from the synchronous registers related thereto. Before all of the task processings have been terminated in the same group, any processors in the same group which have already terminated their task processings progress the execution of the next tasks until they access for the first time a data sharing circuit for holding data shared among the processors.

Abstract: A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each constituted of pages for storing data which are unlikely to give rise to interference between pages. The DRAM of each group is constituted as a memory system which responds to page access. The memory access devices are provided separately for the memory system of each group. Each memory access device has a memory means which, in response to an access designating a page address of the memory system associated therewith, stores an old page address designated at least one access earlier, and judging means which, in response to said page address access, judges whether or not the new page address designated by said access coincides with said old page address stored in said storage means.

Abstract: A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a dual-port RAM accessible from said CPUs, and a common bus switch circuit for connecting any one of said CPUs to a common bus shared by said CPUs.

Abstract: A digital information transmission apparatus and an information transmission bus system thereof capable of quickly stabilizing a signal on a bus. The apparatus outputs to a bus, in a bus cycle identical to a bus cycle in which a digital information input system reads desired digital information, information items identical to the desired digital information read by the digital information input system respectively from the buffers of at least two digital information output systems of a plurality of digital information output systems.

Abstract: A synchronous apparatus for synchronizing a plurality of processors includes: a register for storing information regarding a group of processors executing parallel processing for associated tasks; a unit for making active the task end information of a processor; a comparator for comparing the information stored in the register belonging to the group with the task end information to check if a synchronization in the group has been completed; a signal line for transferring the task end information to the comparator; and a unit for transferring a comparison result by the comparator to the processor.

Abstract: A first processor outputs a series of macro instruction steps which are obtained by dividing an executing sequence of instructions to specify arithmetic operating processes to proper executing units and to time-sequentially output a macro instruction to indicate the execution of each of the macro instruction steps divided; a second processor takes the series of macro instruction steps from the first processor and output instructions included in the macro instruction step of the relevant step in response to the input of the macro instruction.

Abstract: A function-distributed control apparatus comprises a first bus, a second bus, and at least one base processor element which includes a first main processing unit connected to at least the first bus, a second main processing unit connected to at least the second bus, and a dual-port memory with a mutual interrupt circuit connected to both these main processing units for communications between them. The first bus and the first main processing unit are chiefly for intelligent processing required for controlling a machine, while the second bus and the second main processing unit are chiefly for motion control of the machine. Those buses are also connected to various intelligent subsystems each including a processing unit and a dual-port memory with a mutual interrupt circuit for communications with the base processor element.

Abstract: Method and apparatus for floating point operation for calculating an approximate solution in a given argument of a function. An operation unit for carrying out floating point logical operation and floating point multiplication, a first memory for storing data necessary for operation and data produced in a course of operation, a second memory for storing a microprogram for controlling a process of operation of the operation unit, a micro-sequencer for issuing a control command necessary for the operation unit to carry out the operation, in accordance with the microprogram, a third memory for storing a table of solutions of coefficient functions in the series polynomial approximate equation of the function including a coefficient function consisting of numeric logic operation or multiplication operation, and an address latch for designating an address of the solution of the series expansion corresponding to the given argument of the function in the third memory are provided.

Abstract: A control apparatus for controlling a controlled object including controlled elements comprises a host processor, a plurality of slave modules and a communication network for providing communication between the host processor and the slave modules. The host processor interprets a control program to generate commands for the controlled elements in response to demands send from the slave modules. These commands are sent via the communication network to the respective slave modules. Each slave module is allotted to a controlled element and has a processor which interprets and executes the commands for its allotted controlled element and generates a demand upon finishing the execution of a command. This demand is sent via the communication network to the host processor and causes the next command to be generated.