Abstract: The solid-state imaging device includes: a first node for receiving a first signal from outside the solid-state imaging device; a second node for receiving a second signal from outside the solid-state imaging device; a test signal selection circuit for outputting the first signal received at the first node and the second signal received at the second node as a test signal by switching between the first and second signals at desired timing; and a test signal input circuit for supplying the test signal from the test signal selection circuit to an input of the A/D converter.

Abstract: In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed.

Abstract: A semiconductor device 10a includes a normal circuit 11 and a voltage fluctuation detection circuit 12a connected to a power supply 100 in common with the normal circuit 11. The voltage fluctuation detection circuit 12a includes an inverting amplifier 13a, a switching element 14, which is connected between input and output terminals of the inverting amplifier 13a, and a capacitance element 15 connected to the input terminal of the inverting amplifier 13a. After the normal circuit 11 and the switching element 14 are set to an operating state and ON state, respectively, when the switching element 14 is set to OFF state at an arbitrary time, charge corresponding to a power supply voltage Vc0 at that time accumulates in the capacitance element 15.

Abstract: The solid-state imaging device includes: a first node for receiving a first signal from outside the solid-state imaging device; a second node for receiving a second signal from outside the solid-state imaging device; a test signal selection circuit for outputting the first signal received at the first node and the second signal received at the second node as a test signal by switching between the first and second signals at desired timing; and a test signal input circuit for supplying the test signal from the test signal selection circuit to an input of the A/D converter.

Abstract: In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed.

Abstract: The semiconductor device includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.

Abstract: A semiconductor device includes: an A/D converter; a digital processing circuit for performing processing based on conversion results from the A/D converter; a first test circuit for performing operation processing for checking a nonlinearity error (INLE) of the conversion results from the A/D converter; and a second test circuit for performing operation processing for checking a differential nonlinearity error (DNLE) of the conversion results from the A/D converter. The first test circuit performs only part of the operation processing for checking the nonlinearity error (INLE) of the conversion results from the A/D converter. The second test circuit performs only part of the operation processing for checking the differential nonlinearity error (DNLE) of the conversion results from the A/D converter.

Abstract: A semiconductor device 10a includes a normal circuit 11 and a voltage fluctuation detection circuit 12a connected to a power supply 100 in common with the normal circuit 11. The voltage fluctuation detection circuit 12a includes an inverting amplifier 13a, a switching element 14, which is connected between input and output terminals of the inverting amplifier 13a, and a capacitance element 15 connected to the input terminal of the inverting amplifier 13a. After the normal circuit 11 and the switching element 14 are set to an operating state and ON state, respectively, when the switching element 14 is set to OFF state at an arbitrary time, charge corresponding to a power supply voltage Vc0 at that time accumulates in the capacitance element 15.

Abstract: The semiconductor device includes: an A/D conversion circuit; a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; and an output terminal for testing for outputting the conversion results of the A/D conversion circuit externally. The output of the conversion results from the output terminal for testing is made at timing that is different from timing of other conversion operation of which conversion results are to be outputted later and is longer in cycle than timing of conversion operation.

Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.

Abstract: The semiconductor device of the present invention includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.

Abstract: A semiconductor device includes: an A/D converter; a digital processing circuit for performing processing based on conversion results from the A/D converter; a first test circuit for performing operation processing for checking a nonlinearity error (INLE) of the conversion results from the A/D converter; and a second test circuit for performing operation processing for checking a differential nonlinearity error (DNLE) of the conversion results from the A/D converter. The first test circuit performs only part of the operation processing for checking the nonlinearity error (INLE) of the conversion results from the A/D converter. The second test circuit performs only part of the operation processing for checking the differential nonlinearity error (DNLE) of the conversion results from the A/D converter.

Abstract: The semiconductor device includes: an A/D conversion circuit; a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; and an output terminal for testing for outputting the conversion results of the A/D conversion circuit externally. The output of the conversion results from the output terminal for testing is made at timing that is different from timing of other conversion operation of which conversion results are to be outputted later and is longer in cycle than timing of conversion operation.

Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.

Abstract: An anlog boundary scan compliant integrated circuit system carries out a test more reliably and cuts down on power dissipated during normal operation. To perform a test of whether or not an interconnect is connected normally between integrated circuits, multiple logic circuits with mutually different input threshold voltages are provided to detect the logical level of a potential at a terminal, thereby improving the reliability of the test. Potential fixers and power isolators are optionally provided. During normal operation, the power fixers fix the output potentials of the logic circuits, while the power isolators electrically isolate the logic circuits from the ground. As a result, no current flows through the logic circuits or other circuits in succeeding stages while no tests are carried out.