Patents by Inventor Masaya Hosaka

Masaya Hosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9496275
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: November 15, 2016
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Hiroaki Kouketsu, Masaya Hosaka
  • Publication number: 20150072497
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 12, 2015
    Inventors: Hiroaki KOUKETSU, Masaya HOSAKA
  • Patent number: 8901637
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: December 2, 2014
    Assignee: Spansion LLC
    Inventors: Hiroaki Kouketsu, Masaya Hosaka
  • Patent number: 8530307
    Abstract: There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (18) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor. According to the present invention, it is possible to provide a semiconductor device where elements can be isolated between the word lines (14) and memory cells can be miniaturized, and to provide a fabrication method therefor.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: September 10, 2013
    Assignee: Spansion LLC
    Inventor: Masaya Hosaka
  • Publication number: 20120070951
    Abstract: There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (18) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor.
    Type: Application
    Filed: December 21, 2010
    Publication date: March 22, 2012
    Inventor: Masaya HOSAKA
  • Patent number: 7915661
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: March 29, 2011
    Assignee: Spansion LLC
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Patent number: 7880218
    Abstract: There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (16) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor. According to the present invention, it is possible to provide a semiconductor device where elements can be isolated between the word lines (14) and memory cells can be miniaturized, and to provide a fabrication method therefor.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: February 1, 2011
    Assignee: Spansion LLC
    Inventor: Masaya Hosaka
  • Publication number: 20100001333
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor deice and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Application
    Filed: August 18, 2009
    Publication date: January 7, 2010
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Patent number: 7589371
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: September 15, 2009
    Assignee: Spansion LLC
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Publication number: 20070105308
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor deice and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Application
    Filed: August 30, 2006
    Publication date: May 10, 2007
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Publication number: 20060291262
    Abstract: There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (16) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor. According to the present invention, it is possible to provide a semiconductor device where elements can be isolated between the word lines (14) and memory cells can be miniaturized, and to provide a fabrication method therefor.
    Type: Application
    Filed: June 28, 2006
    Publication date: December 28, 2006
    Inventor: Masaya Hosaka
  • Publication number: 20060244037
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Application
    Filed: January 24, 2006
    Publication date: November 2, 2006
    Inventors: Hiroaki Kouketsu, Masaya Hosaka