Abstract: Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.

Abstract: Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.

Abstract: An object of the present invention is that, in a semiconductor memory device having both a redundant circuit and a diagnostic circuit, a memory test for detecting positions of defective memory cells in order to replace the defective memory cells with the redundant circuit can be easily carried out by using the diagnostic circuit. A semiconductor memory device of the present invention includes a normal memory portion, a redundant circuit to replace defective memory cells of the normal memory portion by a units of a word line or a bit line, and a self-diagnostic circuit, and further, in order to realize the object, the device includes a defective cell position storage circuit for storing position information of each defective memory cell when the self-diagnostic circuit detects defective memory cells, and an output circuit for converting position information stored in the defective cell position storage circuit into serial data and outputting the position information.

Abstract: A semiconductor device includes a semiconductor chip, an I/O-cell circuit having a transistor-array part. The semiconductor device further includes a first group of bonding pads and a second group of bonding pads. The first group of bonding pads is connected with the I/O-cell circuit and is formed in a first pad-forming area arranged along an outer side of the transistor-array part in the I/O-cell circuit. And the second group of bonding pads is connected with the I/O-cell circuit and is formed in a second pad-forming area along an inner side of the transistor-array part in the I/O-cell circuit.

Abstract: A semiconductor circuit includes a plurality of first power supply lines which are arranged parallel to each other, a plurality of second power supply lines which are arranged parallel to each other and supplying a power supply voltage different from that supplied by the first power supply lines, where the first and second power supply lines run parallel to each other in a first direction, a first cell made up of the same number of first p-channel transistors and first n-channel transistors which are respectively coupled to the first and second power supply lines, where the first p-channel transistors and the first n-channel transistors are alternately arranged in a second direction and have the same size, and a second cell made up of a different number of second p-channel transistors and second n-channel transistors which are respectively coupled to the first and second power supply lines.