Patents by Inventor Masaya Maruo

Masaya Maruo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6002566
    Abstract: An overcurrent protective circuit includes a N-type depletion mode FET, a P-type depletion mode FET, and a switch. The sources of the N-type depletion mode FET and the P-type depletion mode FET are connected to each other. The gate of the N-type depletion mode FET is connected through a resistor to the drain of the P-type depletion mode FET. The gate of the P-type depletion mode FET is connected through a resistor to the drain of the N-type depletion mode FET. The drain of the N-type depletion mode FET is a positive external terminal of the circuit, while the drain of P-type depletion mode FET is a negative external terminal of the circuit. A switch electrically connects and disconnects between the gate of the N-type depletion mode FET and the gate of the P-type depletion mode FET.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: December 14, 1999
    Assignee: SOC Corporation
    Inventors: Hiroo Arikawa, Masaya Maruo
  • Patent number: 5696659
    Abstract: An overcurrent protective circuit in which the source of an N-type depletion MOS (1) is connected to the source of a P-type depletion MOS (2), the gate of the N-type depletion MOS (1) to the drain of the P-type depletion MOS (2) through a resistor and others, and the gate of the P-type depletion MOS (2) is connected to the drain of the N-type depletion MOS (1) through a resistor and others. A semiconductor circuit to which such an overcurrent protective circuit is connected in parallel through a rated value correcting circuit. Also, this invention provides an overcurrent cut-off circuit which operates, fundamentally, on the same cut-off principle as that of the above-mentioned overcurrent protective circuit and which constitutes an enhanced MOS. Then, by arranging the gate circuit so that the gate voltage does not become greater than a certain value, the overcurrent is suppressed to approximately 1.5 to 2 times the rated current, thus effectuating the cut-off.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: December 9, 1997
    Inventor: Masaya Maruo
  • Patent number: 4219794
    Abstract: A fusible element for use in fuse construction wherein the fusible element is made of an elongated, heat-conductive metal or alloy having regions of reduced cross sectional area, including a middle reduced region and two reduced intermediate regions, each of said reduced regions being disposed between two unreduced regions of the fusible element. The dimensions (width and length) of the reduced regions are selected to optimize the performance of the fusible elements.Another embodiment of the invention contemplates a fusible element with a plurality of reduced regions having specified relative dimensions for improved performance characteristics.
    Type: Grant
    Filed: August 15, 1978
    Date of Patent: August 26, 1980
    Assignee: San-O Industrial Corporation
    Inventors: Hiroo Arikawa, Masaya Maruo, Yasutada Yuza
  • Patent number: 4146861
    Abstract: A novel fuse arrangement for electrical and electronic circuits is provided having shorter arcing time and arc-extinguishing time as compared to the prior art fuses. The fuse arrangement described herein comprises a pair of electrodes having contact terminals for connection to the circuit and a support member preferably disposed triangularly relative to the electrodes. In one embodiment, a fusible wire elment is stretched between the electrodes and has its mid portion supported by the support member. The support member is made from a material of large heat capacity and high thermal conductivity to provide a heat dissipating surface for the heat generated in the fusible wire element.
    Type: Grant
    Filed: July 18, 1977
    Date of Patent: March 27, 1979
    Assignee: San-O Industrial Corp.
    Inventors: Hiroo Arikawa, Akira Taniguchi, Masaya Maruo
  • Patent number: 4122426
    Abstract: A time-lag fuse constructed so that a fuse element is wound on a core member made of a ceramic material having high thermal conductivity, for example, a material comprising high weight per cent aluminum oxide (Al.sub.2 O.sub.3, 85 - 100 wt.%). The fuse has excellent time-lag characteristics imparted by the strong heat-absorbing action of said high weight per cent aluminum oxide.
    Type: Grant
    Filed: January 24, 1977
    Date of Patent: October 24, 1978
    Assignee: San-O Industrial Corp.
    Inventor: Masaya Maruo
  • Patent number: 4100523
    Abstract: A time-lag fuse is provided which exhibits improved breaking capacity due to its novel construction. It comprises a fuse element which is securely positioned within an insulating cylindrical tube such as a glass cartridge, and a plurality of sintered ceramic bodies (e.g., cylindrical or polygonal) are circumferentially disposed within said tube so as to define a space therewith to achieve the required fusing and time-lag characteristics. The sintered ceramic bodies are arranged so as to define plurality of spaces between adjacent pairs of the ceramic bodies and the insulating tube in order to buffer the pressure created by arcing between the ceramic bodies and the insulating tube during a current overload.
    Type: Grant
    Filed: November 19, 1976
    Date of Patent: July 11, 1978
    Assignee: San-O Industrial Co., Ltd.
    Inventors: Hiroo Arikawa, Masaya Maruo
  • Patent number: 4057774
    Abstract: A time-delay fuse is provided comprising a glass or ceramic tube sealed at both ends with sealing means such as, e.g., ferrules. An elongated generally cylindrical core member, made from a highly heat conductive material (a sintered blend of aluminum oxide and magnesium oxide spinel), is diagonally disposed in said tube and rigidly fixed at both ends in intimate contact with said sealing means. The fuse also comprises a wire strand spirally wound on said elongated core member. The wire strand is made by winding a first metallic wire element over a second mutually fusible wire element and is soldered at both ends with a high melting solder element.
    Type: Grant
    Filed: April 16, 1976
    Date of Patent: November 8, 1977
    Inventors: Hiroo Arikawa, Fumitake Akiyama, Masaya Maruo
  • Patent number: 4034329
    Abstract: A time-delay fuse is provided comprising a glass or ceramic tube sealed at both ends with a sealing means such as, e.g., ferrules. The fuse also comprises a generally cylindrical core member of poor heat conductivity (e.g., porous sintered mixture of alumina and clay), and a fusible high melting wire element wound densely on the middle region of said core member, thence sparsely toward the terminals and again densely at the ends where the fusible wire element is soldered by a high-melting solder element.
    Type: Grant
    Filed: April 30, 1976
    Date of Patent: July 5, 1977
    Inventors: Hiroo Arikawa, Masaya Maruo