Abstract: A camera shake measurement system includes a display unit for sequentially displaying a plurality of distinguishable test patterns, a first storage unit for storing as a template each of the plurality of test patterns to be displayed, a second storage unit for storing a composite image produced by photographing at least two test patterns as still images from the plurality of test patterns to be sequentially displayed by a photographing apparatus, and a pattern recognition unit for recognizing images that match each of the templates from the composite image by calling the templates from the first storage unit, calling the composite image from the second storage unit, and moving, for each of the called templates, the template while superposing the template on the composite image.

Abstract: A camera shake measurement system includes a display unit for sequentially displaying a plurality of distinguishable test patterns, a first storage unit for storing as a template each of the plurality of test patterns to be displayed, a second storage unit for storing a composite image produced by photographing at least two test patterns as still images from the plurality of test patterns to be sequentially displayed by a photographing apparatus, and a pattern recognition unit for recognizing images that match each of the templates from the composite image by calling the templates from the first storage unit, calling the composite image from the second storage unit, and moving, for each of the called templates, the template while superposing the template on the composite image.

Abstract: Adjacent pixels in a pixel circuit of an imaging device use a primary capacitance, an amplifying transistor, a reset switch and a selection switch in common. Each pixel has a photodiode and a transfer switch having first and second gates provided on the photodiode side and the primary capacitance side, respectively. In a pixel downsampling read mode, the first and second gate voltages of each pixel to be discarded are brought to high level, and thereafter the first and second gate voltages of each pixel to be read are brought to high level, to transfer charge generated in the photodiode of the pixel to be read to the primary capacitance and the photodiode in each pixel to be discarded. This enables reduction of the potential of the primary capacitance, and hence reduction of the pixel sensitivity than using only the primary capacitance to store charge transferred from the transfer switch.

Abstract: In an imaging device having an all-pixel read mode for reading signals from all pixels and a pixel downsampling read mode for reading signals by appropriately discarding pixels, adjacent ones of pixels use a floating diffusion capacitance, an amplifying transistor, a reset switch and a selection switch in common. In the pixel downsampling read mode, not only a primary capacitance but also a photodiode in each pixel to be discarded are used as capacitances for storing signal charges transferred from transfer switches. This makes it possible to lower the gate voltage of the amplifying transistor as compared with the case of using only the primary capacitance as a capacitance for storing signal charges transferred from a transfer switch to reduce the sensitivity of the pixels, thereby reducing the occurrence of flicker.

Abstract: Adjacent pixels in a pixel circuit of an imaging device use a primary capacitance, an amplifying transistor, a reset switch and a selection switch in common. Each pixel has a photodiode and a transfer switch having first and second gates provided on the photodiode side and the primary capacitance side, respectively. In a pixel downsampling read mode, the first and second gate voltages of each pixel to be discarded are brought to high level, and thereafter the first and second gate voltages of each pixel to be read are brought to high level, to transfer charge generated in the photodiode of the pixel to be read to the primary capacitance and the photodiode in each pixel to be discarded. This enables reduction of the potential of the primary capacitance, and hence reduction of the pixel sensitivity than using only the primary capacitance to store charge transferred from the transfer switch.

Abstract: In an imaging device having an all-pixel read mode for reading signals from all pixels and a pixel downsampling read mode for reading signals by appropriately discarding pixels, adjacent ones of pixels use a floating diffusion capacitance, an amplifying transistor, a reset switch and a selection switch in common. In the pixel downsampling read mode, not only a primary capacitance but also a photodiode in each pixel to be discarded are used as capacitances for storing signal charges transferred from transfer switches. This makes it possible to lower the gate voltage of the amplifying transistor as compared with the case of using only the primary capacitance as a capacitance for storing signal charges transferred from a transfer switch to reduce the sensitivity of the pixels, thereby reducing the occurrence of flicker.

Abstract: Predetermined multiple points of the front passenger seat and its periphery are irradiated with spot beams, caught with a camera, and distances are measured based on the irradiation position of the spot beams. Conversely, the characteristics for each status of use of the seat such as the shapes of the contour of the seat or the contour of a child seat are detected from the picture information caught with the camera. The status of use of the seat is decided based the characteristics for each status of use and the distance information that was previously measured. Based on this decision, the operation of a passive safety device such as an air bag device is controlled.

Abstract: A photodetector device for converting incident light to an electrical signal has two pn junctions or two MOS junctions fabricated in a silicon substrate. Preferably, a control terminal is provided between the two junctions. A photodetection circuit including a photodetector device has a variable sensitivity and can change the polarity of the output of the photodetector device. For example, the photodetection circuits may have a circuit for providing a bias voltage of one of the two polarities to the photodetector device. The photodetection circuit may have a circuit for changing the polarity of the output signal from the photodetector device.

Abstract: A photodetector has a semiconductor substrate which produces light-induced charge upon the absorption of incident light. A first electrode and a second electrode are attached to the surface of the semiconductor substrate so as to form metal-semiconductor junctions. When control voltage V.sub.B, which is variable in a positive range through a negative range, is applied to the first electrode, a photocurrent flows through the second electrode and depletion layers are formed in the surface of the semiconductor substrate. The control voltage V.sub.B applied to the first electrode increases the expanse of one of the depletion layers relative to that of the other to cause the light-induced charge to drift toward one of the depletion layers or the other. Consequently, a positive or negative current is delivered through the second electrode. Thus, the photosensitivity of the photodetector can be controlled by the control voltage V.sub.B.

Abstract: An information retrieval system allowing the user to build a database or to retrieve data therefrom based on vague retrieval-designating data without becoming aware of the database structure. The system comprises a neural network, a memory, an interface part and a CRT. The neural network stores data designating electronic still pictures contained in the memory. When data for designating retrieval are input, the interface part groups the data into such categories as the place where the desired picture was taken and the date on which it was taken, and supplies the neural network with the categorized input data. In turn, the neural network outputs by association the data corresponding to the input data. Given the data from the network, the memory outputs the relevant electronic still picture to the CRT for display.

Abstract: An intelligence information processing system is composed of an associative memory and a serial processing-type computer. Input pattern information is associated with the associative memory, and pattern recognition based on the computer evaluates an associative output. In accordance with this evaluation, an associative and restrictive condition is repeatedly added to the energy function of a neural network constituting the associative memory, thereby converging the associative output on a stable state of the energy. The converged associative output is verified with intelligence information stored in a computer memory. The associative and restrictive condition is again repeatedly added to the energy function in accordance with the verification so as to produce an output from the system.

Abstract: The knowledge information processing system includes a first and second associative memory unit groups. The associative memory units of the first associative memory unit group 1 associates a plurality of distinct features to the input pattern 20. In response to the combination of associated outputs from the first associative memory unit group 1, the second associative memory unit group 4 evaluates and associates features corresponding to those associated by the first associative memory unit group 1. The logical operation unit group 6 compares the associated outputs of the first associative memory unit group 1 with those of the second to judge whether or not corresponding associated outputs agree with each other. If the corresponding associated outputs do not agree, the logical operation unit group 6 outputs feedback information items for correcting the energy functions of the first associative memory unit group 1, thereby repeating the association and the evaluation process.

Abstract: An intelligence information processing system is composed of an associative memory and a serial processing-type computer. Input pattern information is associated with the associative memory, and pattern recognition based on the computer evaluates an associative output. In accordance with this evaluation, an associative and restrictive condition is repeatedly added to the energy function of a neural network constituting the associative memory, thereby converging the associative output on a stable state of the energy. The converged associative output is verified with intelligence information stored in a computer memory. The associative and restrictive condition is again repeatedly added to the energy function in accordance with the verification so as to produce an output from the system.

Abstract: An optical computer for performing product and/or sum operations on input vector information and matrix information includes an array of light emitting elements, the array having a plurality of columns and a plurality of rows. Input circuitry is provided for supplying input vector information to the array while matrix circuitry is provided for dynamically applying matrix information to the array. Logic circuitry is provided for performing one of a logical product and a logical sum operation on the input vector information and the matrix information and for generating an output thereof.

Abstract: An optical neural network which imitates a biological neural network, to provide an associative and/or pattern recognition function, is made of light emitting elements to represent an input neuron state vector, a correlation matrix which modulates light according to stored vector information, light receiving elements, an accumulator and a comparator to perform a threshold function. A stored vector closest to an input vector can be found from a large amount of information without increasing the system size by dividing the correlation matrix and the input neuron state vector with time division techniques, frequency modulation or phase modulation techniques. Positive and negative valves can also be provided with similar techniques.