Abstract: Provided is a susceptor, capable of preventing occurrence of scratches on the back surface of a wafer attributable to lift pins, and reducing unevenness of the in-surface temperature distribution of the wafer. A susceptor according to one embodiment of this disclosure has a susceptor main body and a plate-shaped member, and when a wafer is conveyed, the front surface of the plate-shaped member ascended by lift pins supports the central part of the back surface of the wafer by surface contact. A separation space between the plate-shaped member and the susceptor main body, in a state in which the plate-shaped member is placed on the recessed part, enters further into the central side of the plate-shaped member, in a direction from the front surface to the back surface of the susceptor.

Abstract: Provided is a lift pin for an epitaxial growth apparatus, which can prevent the back surface of a silicon wafer from being damaged by the lift pin, reduce emission of dust due to the rubbing of the lift pin against the wall surface of a through hole in a susceptor, and prevent peeling of glassy carbon. The lift pin has a straight trunk part to be inserted through the through hole; a head part to be made to abut a silicon wafer; and a cover part covering at least a top of the head part. The straight trunk part and the head part are made of a porous body, the cover part is made of a carbon-based covering material, and at least part of voids of the porous body of the head part is filled with the cover part.

Abstract: An epitaxial growth device includes; a chamber; a susceptor; a supporting shaft, having a main column located coaxially with the center of the susceptor and supporting arms; and a lift pin, at least the surface layer region of the lift pin is made of a material having a hardness lower than the susceptor, the lift pin has a straight trunk part upper region configured to pass through the through-hole of the susceptor and having a surface roughness of from not less than 0.1 ?m to not more than 0.3 ?m, and the lift pin has a straight trunk part lower region configured to pass through the through-hole of the supporting arm and having a surface roughness of from not less than 1 ?m to not more than 10 ?m.

Abstract: Provided is a lift pin for an epitaxial growth apparatus, which can prevent the back surface of a silicon wafer from being damaged by the lift pin, reduce emission of dust due to the rubbing of the lift pin against the wall surface of a through hole in a susceptor, and prevent peeling of glassy carbon. The lift pin has a straight trunk part to be inserted through the through hole; a head part to be made to abut a silicon wafer; and a cover part covering at least a top of the head part. The straight trunk part and the head part are made of a porous body, the cover part is made of a carbon-based covering material, and at least part of voids of the porous body of the head part is filled with the cover part.

Abstract: An epitaxial growth device includes; a chamber; a susceptor; a supporting shaft, having a main column located coaxially with the center of the susceptor and supporting arms; and a lift pin, at least the surface layer region of the lift pin is made of a material having a hardness lower than the susceptor, the lift pin has a straight trunk part upper region configured to pass through the through-hole of the susceptor and having a surface roughness of from not less than 0.1 ?m to not more than 0.3 ?m, and the lift pin has a straight trunk part lower region configured to pass through the through-hole of the supporting arm and having a surface roughness of from not less than 1 ?m to not more than 10 ?m.

Abstract: Provided is a susceptor, capable of preventing occurrence of scratches on the back surface of a wafer attributable to lift pins, and reducing unevenness of the in-surface temperature distribution of the wafer. A susceptor according to one embodiment of this disclosure has a susceptor main body and a plate-shaped member, and when a wafer is conveyed, the front surface of the plate-shaped member ascended by lift pins supports the central part of the back surface of the wafer by surface contact. A separation space between the plate-shaped member and the susceptor main body, in a state in which the plate-shaped member is placed on the recessed part, enters further into the central side of the plate-shaped member, in a direction from the front surface to the back surface of the susceptor.

Abstract: A susceptor having a recessed portion and a ring-like step portion is arranged in a reaction chamber, and a plurality of through bores are formed in a bottom wall in the recessed portion excluding the step portion. A lift pin inserted in each of the through bores temporarily holds a wafer, then a lower surface of an outer peripheral portion of the wafer is mounted on the step portion to accommodate the wafer in the recessed portion, and a raw material gas is circulated in the reaction chamber to form an epitaxial layer on a wafer surface in the recessed portion. When forming the epitaxial layer on the wafer surface, the lift pin protrudes upwards from an upper surface of the bottom wall, and a height h of a top portion of the lift pin based on the upper surface of the bottom wall as a reference is set to the range from a position where the height h exceeds 0 mm to a position immediately before the lift pin comes into contact with the wafer.

Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <100> direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.

Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <100> direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.

Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <110 > direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100 } wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.

Abstract: A susceptor having a recessed portion and a ring-like step portion is arranged in a reaction chamber, and a plurality of through bores are formed in a bottom wall in the recessed portion excluding the step portion. A lift pin inserted in each of the through bores temporarily holds a wafer, then a lower surface of an outer peripheral portion of the wafer is mounted on the step portion to accommodate the wafer in the recessed portion, and a raw material gas is circulated in the reaction chamber to form an epitaxial layer on a wafer surface in the recessed portion. When forming the epitaxial layer on the wafer surface, the lift pin protrudes upwards from an upper surface of the bottom wall, and a height h of a top portion of the lift pin based on the upper surface of the bottom wall as a reference is set to the range from a position where the height h exceeds 0 mm to a position immediately before the lift pin comes into contact with the wafer.

Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <110> direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.

Abstract: Solder joints are formed on external electrodes of a semiconductor device, such as a ball grid array package or flip chip or the like, and higher solder joints are formed on the external electrodes. Each solder joint consists of a plurality of solder bumps, such as a first solder bump and a second solder bump. The process includes the steps of forming a first solder bump on an electrode, the electrode being electrically connected with a terminal of an electronic circuit, applying a first non-conductive material onto the first solder bump so as to encompass with the first non-conductive material the exposed area of the first solder bump except for a top portion of the first solder bump, and forming a second solder bump on the top portion of the first solder bump. A semiconductor device having solder joints higher than the single greatest possible solder ball for a given pitch and pad area is fabricated.