Patents by Inventor Masaya Takizawa

Masaya Takizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11792927
    Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: October 17, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Rie Mizutani, Noriyoshi Shimizu, Hiroshi Taneda, Masaya Takizawa, Yoshiki Akiyama
  • Patent number: 11729914
    Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: August 15, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO.. LTD.
    Inventors: Hiroshi Taneda, Noriyoshi Shimizu, Rie Mizutani, Masaya Takizawa, Yoshiki Akiyama
  • Patent number: 11716810
    Abstract: A wiring board includes a first interconnect structure including a first interconnect layer, and a first insulating layer including a non-photosensitive thermosetting resin as a main component thereof, a second interconnect structure including second interconnect layers, and second insulating layers including a photosensitive resin as a main component thereof, and laminated on the first interconnect structure, and an encapsulating resin layer including a non-photosensitive thermosetting resin as a main component thereof, and laminated on an uppermost second insulating layer. An uppermost second interconnect layer includes a pad protruding from the uppermost second insulating layer. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad. Thermal expansion coefficients of the first insulating layer and the encapsulating resin layer are lower than that of the second insulating layers.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: August 1, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masaya Takizawa, Rie Mizutani, Hiroshi Taneda, Yoshiki Akiyama, Noriyoshi Shimizu
  • Publication number: 20230066839
    Abstract: A wiring board includes an interconnect structure including a plurality of interconnect layers, and a plurality of insulating layers having a photosensitive resin as a main component thereof, and an encapsulating resin layer having a non-photosensitive thermosetting resin as a main component thereof, laminated on an uppermost insulating layer of the plurality of insulating layers. An uppermost interconnect layer of the plurality of interconnect layers includes a pad protruding from the uppermost insulating layer. The encapsulating resin layer exposes an upper surface of the pad, and covers at least a portion of a side surface of the pad, and at least a portion of side surfaces of the plurality of insulating layers. The pad is configured to receive a semiconductor chip to be mounted thereon.
    Type: Application
    Filed: August 3, 2022
    Publication date: March 2, 2023
    Inventors: Hiroshi TANEDA, Noriyoshi SHIMIZU, Rie MIZUTANI, Masaya TAKIZAWA, Yoshiki AKIYAMA
  • Publication number: 20230054390
    Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 23, 2023
    Inventors: Rie MIZUTANI, Noriyoshi SHIMIZU, Hiroshi TANEDA, Masaya TAKIZAWA, Yoshiki AKIYAMA
  • Publication number: 20220361331
    Abstract: A wiring board includes a first interconnect structure including a first interconnect layer, and a first insulating layer including a non-photosensitive thermosetting resin as a main component thereof, a second interconnect structure including second interconnect layers, and second insulating layers including a photosensitive resin as a main component thereof, and laminated on the first interconnect structure, and an encapsulating resin layer including a non-photosensitive thermosetting resin as a main component thereof, and laminated on an uppermost second insulating layer. An uppermost second interconnect layer includes a pad protruding from the uppermost second insulating layer. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad. Thermal expansion coefficients of the first insulating layer and the encapsulating resin layer are lower than that of the second insulating layers.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 10, 2022
    Inventors: Masaya TAKIZAWA, Rie MIZUTANI, Hiroshi TANEDA, Yoshiki AKIYAMA, Noriyoshi SHIMIZU
  • Publication number: 20220361340
    Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 10, 2022
    Inventors: Hiroshi TANEDA, Noriyoshi SHIMIZU, Rie MIZUTANI, Masaya TAKIZAWA, Yoshiki AKIYAMA
  • Patent number: 7230713
    Abstract: The polarization angle ?1 of a polarizer (14) is set, and the reflection intensity S1 in a cross Nicol state and the reference reflection intensity Ref1 of a liquid crystal cell (15) are measured. A different polarization angle ?2 is then set, and the reflection intensity S2 in a cross Nicol state and the reference reflection intensity Ref2 of the liquid crystal cell are measured. The rations S1/Ref1, S2/Ref2 of measured intensities and the ratio S1·Ref2/S2·Ref1 is determined in order to cancel the background components of the reference reflection intensities Ref1, Ref2 thus determining the value of cell gap accurately.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: June 12, 2007
    Assignee: Otsuka Electronics Co., Ltd.
    Inventors: Tomohiro Akada, Masaya Takizawa
  • Publication number: 20040233432
    Abstract: The polarization angle &thgr;1 of a polarizer (14) is set, and the reflection intensity S1 in a cross Nicol state and the reference reflection intensity Ref1 of a liquid crystal cell (15) are measured. A different polarization angle &thgr;2 is then set, and the reflection intensity S2 in a cross Nicol state and the reference reflection intensity Ref2 of the liquid crystal cell are measured. The rations S1/Ref1, S2/Ref2 of measured intensities and the ratio S1·Ref2/S2 Ref1 is determined in order to cancel the background components of the reference reflection intensities Ref1, Ref2 thus determining the value of cell gap accurately (FIG. 1).
    Type: Application
    Filed: July 23, 2003
    Publication date: November 25, 2004
    Inventors: Tomohiro Akada, Masaya Takizawa