Patents by Inventor Masaya Uemura

Masaya Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957689
    Abstract: Provided is a semiconductor apparatus capable of enhancing the withstand voltage while suppressing the enlargement of the chip area. Provided is semiconductor apparatus including: a first terminal to which a high frequency signal is supplied; a second terminal from which the high frequency signal is output; first, second and third switch elements electrically connected in series between the first terminal and the second terminal; a first capacitor provided between the first terminal and a first node between the first switch element and the second switch element; and a second capacitor provided between the first terminal and a second node between the second switch element and the third switch element, in which the capacitance of the first capacitor is greater than the capacitance of the second capacitor.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 23, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kenji Noguchi, Toshiyuki Koimori, Hiroaki Nagano, Masaya Uemura, Megumi Nakayama
  • Publication number: 20200013772
    Abstract: Provided is a semiconductor apparatus capable of enhancing the withstand voltage while suppressing the enlargement of the chip area. Provided is semiconductor apparatus including: a first terminal to which a high frequency signal is supplied; a second terminal from which the high frequency signal is output; first, second and third switch elements electrically connected in series between the first terminal and the second terminal; a first capacitor provided between the first terminal and a first node between the first switch element and the second switch element; and a second capacitor provided between the first terminal and a second node between the second switch element and the third switch element, in which the capacitance of the first capacitor is greater than the capacitance of the second capacitor.
    Type: Application
    Filed: January 31, 2018
    Publication date: January 9, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kenji NOGUCHI, Toshiyuki KOIMORI, Hiroaki NAGANO, Masaya UEMURA, Megumi NAKAYAMA
  • Patent number: 8559203
    Abstract: A power source apparatus includes: a first alternating current line; a second alternating current line; an electric power inputting portion including a rectifying circuit for rectifying an alternating current voltage supplied from an alternating current power source, the electric power inputting portion serving to output the rectified voltage to each of the first and second alternating current lines; a first converter including a switching element for converting the alternating current voltage into a first direct current voltage; a second converter for converting the first direct current voltage obtained in the first converter into a second direct current voltage; and a control circuit for carrying out control for driving at least the switching element of the first converter so as to be turned ON or OFF.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: October 15, 2013
    Assignee: Sony Corporation
    Inventors: Masaya Uemura, Tsutomu Fukuda, Yasushi Katayama
  • Patent number: 8384373
    Abstract: Disclosed herein is an AC line signal detection device including: a semiconductor integrated circuit; and a conversion section adapted to rectify an AC line signal and convert the rectified signal to an input signal to be fed to the semiconductor integrated circuit, wherein the semiconductor integrated circuit includes a monitoring section adapted to divide the AC line signal into a plurality of voltage ranges with at least one reference voltage proportional to the amplitude of the AC line signal to monitor within which voltage range the AC line signal falls; a measuring section adapted to measure a duration for which the AC line signal remains in each of the voltage ranges; and a determination section adapted to determine, based on the monitoring result of the monitoring section and the measurement result of the measuring section, whether the duration for which the AC line signal remains in each of the voltage ranges exceeds a set time which can be set in advance to make a pass/fail determination on the AC l
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: February 26, 2013
    Assignee: Sony Corporation
    Inventors: Hiroyuki Watanabe, Yasushi Katayama, Masaya Uemura
  • Patent number: 7915640
    Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventor: Masaya Uemura
  • Publication number: 20100302808
    Abstract: A power source apparatus includes: a first alternating current line; a second alternating current line; an electric power inputting portion including a rectifying circuit for rectifying an alternating current voltage supplied from an alternating current power source, the electric power inputting portion serving to output the rectified voltage to each of the first and second alternating current lines; a first converter including a switching element for converting the alternating current voltage into a first direct current voltage; a second converter for converting the first direct current voltage obtained in the first converter into a second direct current voltage; and a control circuit for carrying out control for driving at least the switching element of the first converter so as to be turned ON or OFF.
    Type: Application
    Filed: April 26, 2010
    Publication date: December 2, 2010
    Applicant: Sony Corporation
    Inventors: Masaya Uemura, Tsutomu Fukuda, Yasushi Katayama
  • Publication number: 20100284207
    Abstract: Disclosed herein is an AC line signal detection device including: a semiconductor integrated circuit; and a conversion section adapted to rectify an AC line signal and convert the rectified signal to an input signal to be fed to the semiconductor integrated circuit, wherein the semiconductor integrated circuit includes a monitoring section adapted to divide the AC line signal into a plurality of voltage ranges with at least one reference voltage proportional to the amplitude of the AC line signal to monitor within which voltage range the AC line signal falls; a measuring section adapted to measure a duration for which the AC line signal remains in each of the voltage ranges; and a determination section adapted to determine, based on the monitoring result of the monitoring section and the measurement result of the measuring section, whether the duration for which the AC line signal remains in each of the voltage ranges exceeds a set time which can be set in advance to make a pass/fail determination on the AC l
    Type: Application
    Filed: March 22, 2010
    Publication date: November 11, 2010
    Applicant: Sony Corporation
    Inventors: Hiroyuki Watanabe, Yasushi Katayama, Masaya Uemura
  • Patent number: 7462892
    Abstract: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: December 9, 2008
    Assignee: Sony Corporation
    Inventors: Ichiro Hase, Ken Sawada, Masaya Uemura
  • Publication number: 20080203426
    Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.
    Type: Application
    Filed: May 19, 2006
    Publication date: August 28, 2008
    Inventor: Masaya Uemura
  • Publication number: 20070023783
    Abstract: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.
    Type: Application
    Filed: July 24, 2006
    Publication date: February 1, 2007
    Inventors: Ichiro Hase, Ken Sawada, Masaya Uemura