Patents by Inventor Masaya Wajima

Masaya Wajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6865090
    Abstract: An outer coating substrate for an electronic component is constructed to be calcined at a low temperature, and greatly decreases the cost thereof while greatly improving the dimensional precision of the substrate. The outer coating substrate for an electronic component includes a multi-layered substrate including a first material layer that is sintered in a liquid phase and a second material layer that is not sintered at the sintering temperature of the first material layer. The first and second material layers are laminated, and calcined at the calcining temperature of the first material layer.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: March 8, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaya Wajima, Tsuneo Amano, Kenichi Kotani, Kenichi Sakai
  • Patent number: 6839243
    Abstract: An electronic component includes a laminate having a structure in which an element substrate and a sealing substrate are bonded to each other through an adhesive layer, a terminal electrode is arranged on the element substrate so as to be exposed at an end surface of the laminate, an outside electrode is disposed on the outer surface of the sealing substrate, the terminal electrode and the outside electrode are electrically connected to each other through an end surface electrode disposed on the end surface of the laminate, and the thickness of the end surface electrode is between about one half of the thickness of the adhesive layer and about five times of the thickness thereof.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: January 4, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenichi Kotani, Masaya Wajima
  • Patent number: 6835601
    Abstract: An apparatus and method for manufacturing substrate elements includes providing a mother substrate, and forming a plurality of through-holes on first lines and second lines opposing each other across sections on the mother substrate. The sections define each of the substrate elements to be formed. The through-holes on the first lines are disposed alternately with respect to the through-holes on the second lines. Electrodes are also provided on the principal plane of the mother substrate and on the inner surfaces of the through-holes. Then, the mother substrate is cut along cut lines in the vertical and horizontal directions.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: December 28, 2004
    Assignee: Murata Manufacturing Co., LTD
    Inventor: Masaya Wajima
  • Patent number: 6747392
    Abstract: A chip electronic component capable of being mounted with high density while preventing separation of bonded portions caused by solder fillets without requiring a case member having a complicated structure is provided at a low cost. The chip electronic component includes an electronic component element board including a circuit that defines an electronic component therein and having a pair of side surfaces and a lower surface, and a plurality of external electrodes extending over at least one of the side surface and the lower surface of the electronic component element and being electrically connected to the circuit provided therein. The electrode portion provided on the lower surface of the monolithic body as an electronic component element of each external electrode is provided with narrow portions and wide portions provided thereon, and the narrow portion continues to the external electrode portion provided on the side surface thereof.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: June 8, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaya Wajima, Naoshi Bamoto
  • Patent number: 6744179
    Abstract: A piezoelectric resonator includes a piezoelectric resonating element, and a first exterior substrate and a second exterior substrate, laminated over and under, respectively, the piezoelectric resonating element. In the piezoelectric resonator, the first exterior substrate and the second exterior substrate each include a multilayer substrate having at least one layer of an internal electrode.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: June 1, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaya Wajima, Kenichi Kotani
  • Publication number: 20030207546
    Abstract: An apparatus and method for manufacturing substrate elements includes providing a mother substrate, and forming a plurality of through-holes on first lines and second lines opposing each other across sections on the mother substrate. The sections define each of the substrate elements to be formed. The through-holes on the first lines are disposed alternately with respect to the through-holes on the second lines. Electrodes are also provided on the principal plane of the mother substrate and on the inner surfaces of the through-holes. Then, the mother substrate is cut along cut lines in the vertical and horizontal directions.
    Type: Application
    Filed: April 9, 2003
    Publication date: November 6, 2003
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Masaya Wajima
  • Publication number: 20030161122
    Abstract: An electronic component includes a laminate having a structure in which an element substrate and a sealing substrate are bonded to each other through an adhesive layer, a terminal electrode is arranged on the element substrate so as to be exposed at an end surface of the laminate, an outside electrode is disposed on the outer surface of the sealing substrate, the terminal electrode and the outside electrode are electrically connected to each other through an end surface electrode disposed on the end surface of the laminate, and the thickness of the end surface electrode is between about one half of the thickness of the adhesive layer and about five times of the thickness thereof.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 28, 2003
    Inventors: Kenichi Kotani, Masaya Wajima
  • Patent number: 6610925
    Abstract: A surface mounting electronic component with external electrodes has a structure in which plated coatings are laminated on metallic coatings by a wet barrel plating method, so as to achieve reduced variation in thickness of the plated coatings of the plurality of external electrodes and reduced defective component frequency rate, with the result that materials for the plated coatings can be utilized efficiently. A plurality of external electrodes are disposed on the outer surfaces of an electronic component body. Each of the external electrodes includes metallic coatings and plated coatings disposed on the metallic coatings by a wet plating method. The area of each of the plurality of electrodes is approximately the same, and the total of lengths of each of the external electrodes on the edges of the electronic component body is approximately the same.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: August 26, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masaya Wajima
  • Patent number: 6570262
    Abstract: An apparatus and method for manufacturing substrate elements includes providing a mother substrate, and forming a plurality of through-holes on first lines and second lines opposing each other across sections on the mother substrate. The sections define each of the substrate elements to be formed. The through-holes on the first lines are disposed alternately with respect to the through-holes on the second lines. Electrodes are also provided on the principal plane of the mother substrate and on the inner surfaces of the through-holes. Then, the mother substrate is cut along cut lines in the vertical and horizontal directions.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: May 27, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masaya Wajima
  • Patent number: 6525449
    Abstract: In an energy-trapping piezoelectric resonator which utilizes a harmonic in a thickness-extensional vibration mode, first and second excitation electrodes are provided partially on both major surfaces of a piezoelectric substrate such that they are opposed to each other on the front and rear surfaces via the piezoelectric substrate. First and second lead electrodes are connected to the first and second excitation electrodes, and first and second terminal electrodes provided along edges of the piezoelectric substrate are connected to the first and second lead electrodes, respectively. A spurious suppressing electrode section is connected to a portion of at least one of the first and second lead electrodes.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: February 25, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masaya Wajima
  • Publication number: 20020135274
    Abstract: An outer coating substrate for an electronic component is constructed to be calcined at a low temperature, and greatly decreases the cost thereof while greatly improving the dimensional precision of the substrate. The outer coating substrate for an electronic component includes a multi-layered substrate including a first material layer that is sintered in a liquid phase and a second material layer that is not sintered at the sintering temperature of the first material layer. The first and second material layers are laminated, and calcined at the calcining temperature of the first material layer.
    Type: Application
    Filed: April 23, 2002
    Publication date: September 26, 2002
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masaya Wajima, Tsuneo Amano, Kenichi Kotani, Kenichi Sakai
  • Patent number: 6448696
    Abstract: An outer coating substrate for an electronic component is constructed to be calcined at a low temperature, and greatly decreases the cost thereof while greatly improving the dimensional precision of the substrate. The outer coating substrate for an electronic component includes a multi-layered substrate including a first material layer that is sintered in a liquid phase and a second material layer that is not sintered at the sintering temperature of the first material layer. The first and second material layers are laminated, and calcined at the calcining temperature of the first material layer.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: September 10, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaya Wajima, Tsuneo Amano, Kenichi Kotani, Kenichi Sakai
  • Patent number: 6433466
    Abstract: A piezoelectric resonant component is constructed such that it is possible to reduce the thickness of an exterior case member while preventing fracture and chipping of the exterior case member. The piezoelectric resonant component preferably includes exterior substrates defining exterior case members and being stacked on an energy trap type piezoelectric resonant element via adhesive layers disposed therebetween so as to define spaces for allowing for free and unhindered vibration of the piezoelectric vibration portion, and a plurality of external electrodes disposed on the surfaces of the exterior substrates on the opposite side of the surfaces thereof fastened to the piezoelectric resonant element are arranged so as not to overlap with the spaces through the intermediary of the exterior substrates.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 13, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masaya Wajima
  • Patent number: 6373169
    Abstract: A capacitor-containing piezoelectric resonance component is constructed to minimize variations in electrostatic capacitance. The component includes dielectric substrates that are disposed on upper and lower surfaces of an energy-trap type piezoelectric resonance element such that a vibration space is defined. On the dielectric substrates, first and second capacitor-defining electrodes are disposed to define a predetermined gap G in a direction that is substantially parallel to the main surface of the dielectric substrate. The second capacitor-defining electrode overlaps with the vibration space via either the dielectric substrates or portions of the dielectric substrates. When G′ represents the distance between an end portion of the second capacitor-defining electrode and an end portion of the vibratory space along the direction in which the first and the second capacitor-defining electrode oppose each other, one of the expressions G′/G≧1 and G′/G≦−0.4 is satisfied.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: April 16, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masaya Wajima
  • Patent number: 6369335
    Abstract: A method for manufacturing substrate elements includes providing a mother substrate, forming at least one elongated through-hole on the mother substrate such that an entire longitudinal end surface of the first substrate element and a portion of a lateral surface of the second substrate element are exposed, forming an electrode pattern on the inner surface of the at least one elongated through-hole, and cutting the mother substrate along lines extending in the vicinity of the longitudinal ends of the at least one elongated through-hole and in a direction that is substantially perpendicular to the longitudinal axis of the elongated through-hole.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: April 9, 2002
    Assignee: Murata Manufacturing Co., Ltd
    Inventor: Masaya Wajima
  • Publication number: 20010038257
    Abstract: A piezoelectric resonant component is constructed such that it is possible to reduce the thickness of an exterior case member while preventing fracture and chipping of the exterior case member. The piezoelectric resonant component preferably includes exterior substrates defining exterior case members and being stacked on an energy trap type piezoelectric resonant element via adhesive layers disposed therebetween so as to define spaces for allowing for free and unhindered vibration of the piezoelectric vibration portion, and a plurality of external electrodes disposed on the surfaces of the exterior substrates on the opposite side of the surfaces thereof fastened to the piezoelectric resonant element are arranged so as not to overlap with the spaces through the intermediary of the exterior substrates.
    Type: Application
    Filed: March 9, 2001
    Publication date: November 8, 2001
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Masaya Wajima
  • Publication number: 20010030490
    Abstract: A piezoelectric resonator includes a piezoelectric resonating element, and a first exterior substrate and a second exterior substrate, laminated over and under, respectively, the piezoelectric resonating element. In the piezoelectric resonator, the first exterior substrate and the second exterior substrate each include a multilayer substrate having at least one layer of an internal electrode.
    Type: Application
    Filed: December 20, 2000
    Publication date: October 18, 2001
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masaya Wajima, Kenichi Kotani
  • Publication number: 20010024076
    Abstract: An outer coating substrate for an electronic component is constructed to be calcined at a low temperature, and greatly decreases the cost thereof while greatly improving the dimensional precision of the substrate. The outer coating substrate for an electronic component includes a multi-layered substrate including a first material layer that is sintered in a liquid phase and a second material layer that is not sintered at the sintering temperature of the first material layer. The first and second material layers are laminated, and calcined at the calcining temperature of the first material layer.
    Type: Application
    Filed: December 20, 2000
    Publication date: September 27, 2001
    Applicant: Murata Manufacturing Co.,Ltd.
    Inventors: Masaya Wajima, Tsuneo Amano, Kenichi Kotani, Kenichi Sakai
  • Patent number: 6276992
    Abstract: A method of forming a groove on a mother material substrate includes the steps of forming a first layer on a surface of the mother material substrate, the first layer including a chain-polymer material which is soluble in an organic solvent. Then a second layer is formed on the first layer except for a portion where the groove is to be formed. The second layer includes a chain-polymer material having very high resistance to sand blasting. Then a groove is formed by cutting the first layer and the mother material substrate at the portion where the groove is to be formed, by a sand blasting process in which sand is directed from above the second layer downwardly. Then the first and second layers are removed from the mother material by dissolving the first layer using the organic solvent.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: August 21, 2001
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Masuyoshi Houda, Masaya Wajima
  • Patent number: 6274964
    Abstract: A piezoelectric resonator adapted to generate a third harmonic wave of a thickness extensional vibration mode in which the fundamental wave is lead out of the vibrating portion and suppressed effectively. The piezoelectric resonator includes a vibrating portion with vibration electrodes opposing each other in the middle of a piezoelectric plate, lead-out electrodes electrically connected to the vibration electrodes, and a floating electrode disposed along the short side edge on at least one major surface of the piezoelectric plate or in the vicinity of the edge.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: August 14, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Ryuhei Yoshida, Masaya Wajima, Kenichi Sakai