Patents by Inventor Masaya Watanabe

Masaya Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5003468
    Abstract: Mask data in a PSW are latched and sent from a host to a guest are subjected to a logical AND operation with latched data taken from an intervention request field of a state descriptor of the guest machine. The resultant logical product is used for setting the PSW of the guest machine and activating an interception to the host. The overhead of an execution controller managing the state transition between guest-host machines is reduced.
    Type: Grant
    Filed: May 5, 1988
    Date of Patent: March 26, 1991
    Assignees: Hitachi, Ltd., Hitachi Computer Engineering Co.
    Inventors: Masaya Watanabe, Fujio Wakui, Shuichi Abe
  • Patent number: 4816991
    Abstract: An address translation buffer in a virtual machine system is so arranged as to include a state descriptor address field for holding an address of a main memory at which a guest virtual machine state descriptor is located and which is designated by a guest virtual machine execution start instruction in addition to a pair of addresses for address translation. With this arrangement, the guest virtual machine associated with the paired addressed for address translation can be identified, while address translation information for a plurality of guest virtual machines can be simultaneously held in an address translation buffer.
    Type: Grant
    Filed: March 16, 1987
    Date of Patent: March 28, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masaya Watanabe, Shuichi Abe
  • Patent number: 4733344
    Abstract: The data processing apparatus has first and second storages each independently accessible. An instruction unit applies a fetch request on a one-operand instruction to the first storage, and a fetch request on a two-operand instruction to the first and second storages. In case of a fetch request on a two-operand instruction, a storage control unit instructs the instruction unit to produce again a fetch request if one of the first and second storages is busy, and execute reading the operands in the order of decoding of instructions.
    Type: Grant
    Filed: December 24, 1985
    Date of Patent: March 22, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masaya Watanabe, Shuichi Abe