Patents by Inventor Masayasu Iguchi
Masayasu Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9667972Abstract: When compression encoding processing of an image is performed in units of macroblocks using a pipeline structure, an application of a skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on a structure of the pipeline stages, the motion vectors may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. This problem can be solved by (i) calculating all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selecting, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.Type: GrantFiled: November 28, 2014Date of Patent: May 30, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroshi Amano, Takeshi Tanaka, Masaki Maeda, Kenjiro Tsuda, Masayasu Iguchi, Youji Shibahara
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Patent number: 9319698Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected.Type: GrantFiled: September 29, 2014Date of Patent: April 19, 2016Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hiroshi Amano, Masayasu Iguchi
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Patent number: 9042457Abstract: An image decoding apparatus which decodes, in parallel, a coded stream having processing order dependency includes: a slice data predecoding unit which predecodes, on a macroblock group basis, macroblock groups included in the coded stream to generate macroblock decoding information necessary for decoding other macroblock groups; and a first macroblock decoding unit and a second macroblock decoding unit each of which decodes a corresponding one of macroblock groups included in the coded stream in parallel. Each of the macroblock decoding units, when decoding the corresponding one of macroblock groups, uses the macroblock decoding information that has been generated for the other macroblock group.Type: GrantFiled: June 5, 2009Date of Patent: May 26, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiteru Hayashi, Hiroshi Amano, Masayasu Iguchi
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Publication number: 20150085918Abstract: When compression encoding processing of an image is performed in units of macroblocks using a pipeline structure, an application of a skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on a structure of the pipeline stages, the motion vectors may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. This problem can be solved by (i) calculating all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selecting, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.Type: ApplicationFiled: November 28, 2014Publication date: March 26, 2015Inventors: Hiroshi AMANO, Takeshi TANAKA, Masaki MAEDA, Kenjiro TSUDA, Masayasu IGUCHI, Youji SHIBAHARA
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Publication number: 20150016507Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected.Type: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Inventors: Hiroshi AMANO, Masayasu IGUCHI
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Patent number: 8897583Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected.Type: GrantFiled: May 21, 2009Date of Patent: November 25, 2014Assignee: Panasonic CorporationInventors: Hiroshi Amano, Masayasu Iguchi
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Patent number: 8867612Abstract: There is disclosed a decoding method for decoding an incoming bitstream entropy-encoded according to an encoding method based on either of arithmetic encoding algorithm and non-arithmetic encoding algorithm, the incoming bitstream including syntax elements. The decoding method includes a first converting step of converting the incoming bitstream into an intermediate bitstream according to the encoding method, the first converting being capable of being omitted, a buffering step of selecting, according to the encoding method, either the intermediate bitstream or the incoming bitstream to store the selected bitstream onto a memory, and a second converting step of reading the selected bitstream from the memory to convert the read bitstream into syntax elements, the read bitstream being either the intermediate bitstream or the incoming bitstream.Type: GrantFiled: February 25, 2013Date of Patent: October 21, 2014Assignee: Panasonic CorporationInventors: Masayoshi Tojima, Masayasu Iguchi, Kiyofumi Abe, Hiroaki Toida, Takahiro Nishi
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Patent number: 8767833Abstract: Provided is a motion compensating apparatus that includes: a motion compensation position determining unit that determines, based on a motion vector, a position of pixels for which compensated pixels should be generated; a necessary pixel determining unit that determines pixels necessary for performing 6-tap filtering; a data transfer controlling unit that controls the order or the like of taking out data to be transferred; an intermediate pixel storage memory for storing pixel data with half-pixel accuracy; a high-order tap filtering unit that generates pixel data with half-pixel accuracy by successively performing filtering operations in a predetermined direction; and a linear interpolation calculating unit that performs linear interpolation based on the position of pixels to be motion compensated, and generates and outputs pixel data with motion compensation accuracy of less than half-pixel accuracy.Type: GrantFiled: July 18, 2012Date of Patent: July 1, 2014Assignee: Panasonic CorporationInventor: Masayasu Iguchi
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Patent number: 8660189Abstract: A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).Type: GrantFiled: June 17, 2010Date of Patent: February 25, 2014Assignee: Panasonic CorporationInventors: Tadamasa Toma, Shinya Kadono, Masayasu Iguchi, Tomoyuki Okada, Yoshinori Matsui, Satoshi Kondo, Hiroshi Yahata, Wataru Ikeda
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Patent number: 8406308Abstract: An encoding device encoding binary signals using arithmetic-encoding. The encoding device includes a binarization unit binarizing multivalued syntax elements in order to generate the binary signals. The generated binary signals are stored on an intermediate buffer. Further, the encoding device includes an arithmetic-encoding unit performing the arithmetic-encoding on the binary signals stored on the intermediate buffer. Additionally, the generated binary signals are binary representations of values of the multivalued syntax elements.Type: GrantFiled: April 16, 2010Date of Patent: March 26, 2013Assignee: Panasonic CorporationInventors: Masayoshi Tojima, Masayasu Iguchi, Kiyofumi Abe, Hiroaki Toida, Takahiro Nishi
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Publication number: 20120281765Abstract: Provided is a motion compensating apparatus that includes: a motion compensation position determining unit that determines, based on a motion vector, a position of pixels for which compensated pixels should be generated; a necessary pixel determining unit that determines pixels necessary for performing 6-tap filtering; a data transfer controlling unit that controls the order or the like of taking out data to be transferred; an intermediate pixel storage memory for storing pixel data with half-pixel accuracy; a high-order tap filtering unit that generates pixel data with half-pixel accuracy by successively performing filtering operations in a predetermined direction; and a linear interpolation calculating unit that performs linear interpolation based on the position of pixels to be motion compensated, and generates and outputs pixel data with motion compensation accuracy of less than half-pixel accuracy.Type: ApplicationFiled: July 18, 2012Publication date: November 8, 2012Inventor: Masayasu IGUCHI
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Patent number: 8284835Abstract: Provided is a motion compensating apparatus that efficiently generates a motion-compensated pixel by reducing the amount of data to be transmitted from a multi frame memory storing reference pixel data, while minimizing an increase in the scale of a circuit.Type: GrantFiled: March 23, 2005Date of Patent: October 9, 2012Assignee: Panasonic CorporationInventor: Masayasu Iguchi
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Patent number: 8233781Abstract: There is provided an image reproduction apparatus for seamlessly reproducing a connected stream which is obtained by connecting plural streams that are respectively coded by different codec methods. An image reproduction apparatus (100) for reproducing a connected stream which is obtained by connecting plural streams of different codec methods such as an MPEG-2 method and an MPEG-4 AVC method is provided with a stream buffer (102) in which the connected stream Bst is stored, and plural decoders Dd1˜Ddn corresponding to the various kinds of codec methods, and a decoder for decoding each stream in the connected stream Bst that is outputted from the stream buffer (102) is selected from among the plural decoders according to the codec method of each stream.Type: GrantFiled: September 1, 2005Date of Patent: July 31, 2012Assignee: Panasonic CorporationInventors: Takahiro Nishi, Satoshi Kondo, Masayasu Iguchi, Tadamasa Toma, Hisao Sasai, Toshiyasu Sugio
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Patent number: 8208541Abstract: Provided is a motion estimation device in which an amount of pixel data transferred from an external frame memory to an internal reference local memory is reduced. By the motion estimation device, it is possible to reduce a memory capacity and a size or processing of a circuit controlling the pixel transfer. In a reference memory control unit and an internal reference memory, a height of a area to be updated is set to L pixels, where L is power of 2, a logical address segments, whose size is suitable for address calculation, are allocated to picture space, and FIFO management is performs. In another application, an assistance memory is added, and another element other than the assistance memory performs the FIFO management for rectangular areas in an image of a conventional width. As a result, the address calculation is simplified, which makes it possible to reduce an embedded circuit for the reference memory control unit and the internal reference memory.Type: GrantFiled: April 2, 2007Date of Patent: June 26, 2012Assignee: Panasonic CorporationInventors: Masayasu Iguchi, Tatsuro Juri, Takeshi Tanaka
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Patent number: 8179972Abstract: An image decoding device and an encoding device include an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing.Type: GrantFiled: June 7, 2005Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventors: Hidekatsu Ozeki, Masayasu Iguchi, Takahiro Nishi, Hiroaki Toida, Hiroto Tomita, Akihiko Inoue, Takashi Hashimoto
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Publication number: 20120051433Abstract: While temporal and spatial direct modes are both supported, the amount of temporarily-stored direct-mode prediction information is reduced, thereby reducing the memory bus bandwidth. A motion information generator combines a motion vector for an anchor block with the number of a reference picture of the anchor block, thereby generates motion information of the pixel block. A still-state determination unit determines whether or not the pixel block is considered still based on the motion vector for the anchor block and on the number of the reference picture. A selector selectively stores in a memory either an output of the motion information generator or a determination result of the still-state determination unit as direct-mode prediction information of the pixel block. A motion vector predictor predicts a motion vector for the pixel block in direct mode based on the direct-mode prediction information stored in the memory.Type: ApplicationFiled: November 9, 2011Publication date: March 1, 2012Applicant: Panasonic CorporationInventors: Mikiko Roji, Masayasu Iguchi, Kotaro Esaki, Hiroshi Amano
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Patent number: 8085851Abstract: A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).Type: GrantFiled: October 8, 2009Date of Patent: December 27, 2011Assignee: Panasonic CorporationInventors: Tadamasa Toma, Shinya Kadono, Masayasu Iguchi, Tomoyuki Okada, Yoshinori Matsui, Satoshi Kondo, Hiroshi Yahata, Wataru Ikeda
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Patent number: 8081683Abstract: A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data.Type: GrantFiled: April 16, 2010Date of Patent: December 20, 2011Assignee: Panasonic CorporationInventors: Masayoshi Tojima, Masayasu Iguchi, Kiyofumi Abe, Hiroaki Toida, Takahiro Nishi
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Patent number: 8050328Abstract: An image decoding method includes a first storage step of sequentially decoding pictures in a stream, storing a picture to be used as a reference into a picture memory, and managing the picture. Further, the image decoding method includes a determination step of determining whether or not random access reproduction has been designated, a state change step of changing a management state for managing a picture in the picture memory, when the random access reproduction has been designated, and a second storage step of sequentially decoding each of the coded pictures from a random access reproduction destination, storing, into the picture memory, a picture to be used as a reference, and managing the picture. This image decoding method enables the decoding of pictures with reference to an appropriate picture even when random access reproduction is performed.Type: GrantFiled: January 11, 2006Date of Patent: November 1, 2011Assignee: Panasonic CorporationInventors: Masayasu Iguchi, Shinya Kadono, Tadamasa Toma, Kiyofumi Abe
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Publication number: 20110200115Abstract: An image decoding apparatus (40) which decodes, in parallel, a coded stream (Str) having processing order dependency includes: a slice data predecoding unit (402) which predecodes, on a macroblock group basis, macroblock groups included in the coded stream (Str) to generate macroblock decoding information (1001) necessary for decoding other macroblock groups; and a first macroblock decoding unit (404) and a second macroblock decoding unit (405) each of which decodes a corresponding one of macroblock groups included in the coded stream (Str) in parallel. Each of the macroblock decoding units (404, 405), when decoding the corresponding one of macroblock groups, uses the macroblock decoding information (1001) that has been generated for the other macroblock group.Type: ApplicationFiled: June 5, 2009Publication date: August 18, 2011Inventors: Yoshiteru Hayashi, Hiroshi Amano, Masayasu Iguchi