Patents by Inventor Masayasu Iguchi

Masayasu Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9667972
    Abstract: When compression encoding processing of an image is performed in units of macroblocks using a pipeline structure, an application of a skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on a structure of the pipeline stages, the motion vectors may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. This problem can be solved by (i) calculating all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selecting, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: May 30, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshi Amano, Takeshi Tanaka, Masaki Maeda, Kenjiro Tsuda, Masayasu Iguchi, Youji Shibahara
  • Patent number: 9319698
    Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: April 19, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hiroshi Amano, Masayasu Iguchi
  • Patent number: 9042457
    Abstract: An image decoding apparatus which decodes, in parallel, a coded stream having processing order dependency includes: a slice data predecoding unit which predecodes, on a macroblock group basis, macroblock groups included in the coded stream to generate macroblock decoding information necessary for decoding other macroblock groups; and a first macroblock decoding unit and a second macroblock decoding unit each of which decodes a corresponding one of macroblock groups included in the coded stream in parallel. Each of the macroblock decoding units, when decoding the corresponding one of macroblock groups, uses the macroblock decoding information that has been generated for the other macroblock group.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: May 26, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshiteru Hayashi, Hiroshi Amano, Masayasu Iguchi
  • Publication number: 20150085918
    Abstract: When compression encoding processing of an image is performed in units of macroblocks using a pipeline structure, an application of a skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on a structure of the pipeline stages, the motion vectors may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. This problem can be solved by (i) calculating all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selecting, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.
    Type: Application
    Filed: November 28, 2014
    Publication date: March 26, 2015
    Inventors: Hiroshi AMANO, Takeshi TANAKA, Masaki MAEDA, Kenjiro TSUDA, Masayasu IGUCHI, Youji SHIBAHARA
  • Publication number: 20150016507
    Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Hiroshi AMANO, Masayasu IGUCHI
  • Patent number: 8897583
    Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Amano, Masayasu Iguchi
  • Patent number: 8867612
    Abstract: There is disclosed a decoding method for decoding an incoming bitstream entropy-encoded according to an encoding method based on either of arithmetic encoding algorithm and non-arithmetic encoding algorithm, the incoming bitstream including syntax elements. The decoding method includes a first converting step of converting the incoming bitstream into an intermediate bitstream according to the encoding method, the first converting being capable of being omitted, a buffering step of selecting, according to the encoding method, either the intermediate bitstream or the incoming bitstream to store the selected bitstream onto a memory, and a second converting step of reading the selected bitstream from the memory to convert the read bitstream into syntax elements, the read bitstream being either the intermediate bitstream or the incoming bitstream.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventors: Masayoshi Tojima, Masayasu Iguchi, Kiyofumi Abe, Hiroaki Toida, Takahiro Nishi
  • Patent number: 8767833
    Abstract: Provided is a motion compensating apparatus that includes: a motion compensation position determining unit that determines, based on a motion vector, a position of pixels for which compensated pixels should be generated; a necessary pixel determining unit that determines pixels necessary for performing 6-tap filtering; a data transfer controlling unit that controls the order or the like of taking out data to be transferred; an intermediate pixel storage memory for storing pixel data with half-pixel accuracy; a high-order tap filtering unit that generates pixel data with half-pixel accuracy by successively performing filtering operations in a predetermined direction; and a linear interpolation calculating unit that performs linear interpolation based on the position of pixels to be motion compensated, and generates and outputs pixel data with motion compensation accuracy of less than half-pixel accuracy.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Panasonic Corporation
    Inventor: Masayasu Iguchi
  • Patent number: 8660189
    Abstract: A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: February 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Tadamasa Toma, Shinya Kadono, Masayasu Iguchi, Tomoyuki Okada, Yoshinori Matsui, Satoshi Kondo, Hiroshi Yahata, Wataru Ikeda
  • Patent number: 8406308
    Abstract: An encoding device encoding binary signals using arithmetic-encoding. The encoding device includes a binarization unit binarizing multivalued syntax elements in order to generate the binary signals. The generated binary signals are stored on an intermediate buffer. Further, the encoding device includes an arithmetic-encoding unit performing the arithmetic-encoding on the binary signals stored on the intermediate buffer. Additionally, the generated binary signals are binary representations of values of the multivalued syntax elements.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Masayoshi Tojima, Masayasu Iguchi, Kiyofumi Abe, Hiroaki Toida, Takahiro Nishi
  • Publication number: 20120281765
    Abstract: Provided is a motion compensating apparatus that includes: a motion compensation position determining unit that determines, based on a motion vector, a position of pixels for which compensated pixels should be generated; a necessary pixel determining unit that determines pixels necessary for performing 6-tap filtering; a data transfer controlling unit that controls the order or the like of taking out data to be transferred; an intermediate pixel storage memory for storing pixel data with half-pixel accuracy; a high-order tap filtering unit that generates pixel data with half-pixel accuracy by successively performing filtering operations in a predetermined direction; and a linear interpolation calculating unit that performs linear interpolation based on the position of pixels to be motion compensated, and generates and outputs pixel data with motion compensation accuracy of less than half-pixel accuracy.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 8, 2012
    Inventor: Masayasu IGUCHI
  • Patent number: 8284835
    Abstract: Provided is a motion compensating apparatus that efficiently generates a motion-compensated pixel by reducing the amount of data to be transmitted from a multi frame memory storing reference pixel data, while minimizing an increase in the scale of a circuit.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventor: Masayasu Iguchi
  • Patent number: 8233781
    Abstract: There is provided an image reproduction apparatus for seamlessly reproducing a connected stream which is obtained by connecting plural streams that are respectively coded by different codec methods. An image reproduction apparatus (100) for reproducing a connected stream which is obtained by connecting plural streams of different codec methods such as an MPEG-2 method and an MPEG-4 AVC method is provided with a stream buffer (102) in which the connected stream Bst is stored, and plural decoders Dd1˜Ddn corresponding to the various kinds of codec methods, and a decoder for decoding each stream in the connected stream Bst that is outputted from the stream buffer (102) is selected from among the plural decoders according to the codec method of each stream.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: July 31, 2012
    Assignee: Panasonic Corporation
    Inventors: Takahiro Nishi, Satoshi Kondo, Masayasu Iguchi, Tadamasa Toma, Hisao Sasai, Toshiyasu Sugio
  • Patent number: 8208541
    Abstract: Provided is a motion estimation device in which an amount of pixel data transferred from an external frame memory to an internal reference local memory is reduced. By the motion estimation device, it is possible to reduce a memory capacity and a size or processing of a circuit controlling the pixel transfer. In a reference memory control unit and an internal reference memory, a height of a area to be updated is set to L pixels, where L is power of 2, a logical address segments, whose size is suitable for address calculation, are allocated to picture space, and FIFO management is performs. In another application, an assistance memory is added, and another element other than the assistance memory performs the FIFO management for rectangular areas in an image of a conventional width. As a result, the address calculation is simplified, which makes it possible to reduce an embedded circuit for the reference memory control unit and the internal reference memory.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: June 26, 2012
    Assignee: Panasonic Corporation
    Inventors: Masayasu Iguchi, Tatsuro Juri, Takeshi Tanaka
  • Patent number: 8179972
    Abstract: An image decoding device and an encoding device include an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: May 15, 2012
    Assignee: Panasonic Corporation
    Inventors: Hidekatsu Ozeki, Masayasu Iguchi, Takahiro Nishi, Hiroaki Toida, Hiroto Tomita, Akihiko Inoue, Takashi Hashimoto
  • Publication number: 20120051433
    Abstract: While temporal and spatial direct modes are both supported, the amount of temporarily-stored direct-mode prediction information is reduced, thereby reducing the memory bus bandwidth. A motion information generator combines a motion vector for an anchor block with the number of a reference picture of the anchor block, thereby generates motion information of the pixel block. A still-state determination unit determines whether or not the pixel block is considered still based on the motion vector for the anchor block and on the number of the reference picture. A selector selectively stores in a memory either an output of the motion information generator or a determination result of the still-state determination unit as direct-mode prediction information of the pixel block. A motion vector predictor predicts a motion vector for the pixel block in direct mode based on the direct-mode prediction information stored in the memory.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 1, 2012
    Applicant: Panasonic Corporation
    Inventors: Mikiko Roji, Masayasu Iguchi, Kotaro Esaki, Hiroshi Amano
  • Patent number: 8085851
    Abstract: A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: December 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Tadamasa Toma, Shinya Kadono, Masayasu Iguchi, Tomoyuki Okada, Yoshinori Matsui, Satoshi Kondo, Hiroshi Yahata, Wataru Ikeda
  • Patent number: 8081683
    Abstract: A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: December 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Masayoshi Tojima, Masayasu Iguchi, Kiyofumi Abe, Hiroaki Toida, Takahiro Nishi
  • Patent number: 8050328
    Abstract: An image decoding method includes a first storage step of sequentially decoding pictures in a stream, storing a picture to be used as a reference into a picture memory, and managing the picture. Further, the image decoding method includes a determination step of determining whether or not random access reproduction has been designated, a state change step of changing a management state for managing a picture in the picture memory, when the random access reproduction has been designated, and a second storage step of sequentially decoding each of the coded pictures from a random access reproduction destination, storing, into the picture memory, a picture to be used as a reference, and managing the picture. This image decoding method enables the decoding of pictures with reference to an appropriate picture even when random access reproduction is performed.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: November 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Masayasu Iguchi, Shinya Kadono, Tadamasa Toma, Kiyofumi Abe
  • Publication number: 20110200115
    Abstract: An image decoding apparatus (40) which decodes, in parallel, a coded stream (Str) having processing order dependency includes: a slice data predecoding unit (402) which predecodes, on a macroblock group basis, macroblock groups included in the coded stream (Str) to generate macroblock decoding information (1001) necessary for decoding other macroblock groups; and a first macroblock decoding unit (404) and a second macroblock decoding unit (405) each of which decodes a corresponding one of macroblock groups included in the coded stream (Str) in parallel. Each of the macroblock decoding units (404, 405), when decoding the corresponding one of macroblock groups, uses the macroblock decoding information (1001) that has been generated for the other macroblock group.
    Type: Application
    Filed: June 5, 2009
    Publication date: August 18, 2011
    Inventors: Yoshiteru Hayashi, Hiroshi Amano, Masayasu Iguchi