Abstract: A method of adjusting modulation accuracy corrects an I modulation signal and a Q modulation signal without using special hardware when an accurate 90.degree. phase difference between the I modulation signal and the Q modulation signal is not present. The method comprises setting I component correction .DELTA.i for a plurality of phase differences in advance to an I component corrector in accordance with an I signal, which is converted from digital modulation data in a digital data train by a modulator and an IQ converter of a phase error corrector. The method also comprises setting a Q component correction .DELTA.q for a plurality of phase differences in advance to a Q component corrector in accordance with a Q signal, controlling the I component corrector and the Q component corrector by a phase error correction controller, thereby adding the I component correction .DELTA.i and the Q component correction .DELTA.

Abstract: In a logic analyzer including first and second sampling channels operative with different clocks independently, a system for determining sequence in time in which the sampled data are generated in both sampling channels includes a memory interposed between the first and second sampling channels. The memory has a data input supplied with the address data of the first sampling channel, an address input supplied with the address data of the second sampling channel and a data write input supplied with the clock signal of the second sampling channel.

Abstract: A logic analyzer including at least a sampling system for sampling input data with a sampling clock signal comprises a condition decision circuit having inputs supplied with the input data and an internal clock signal for producing a conditioning signal in dependence on the input data in synchronism with the internal clock signal, a clock detection circuit for deciding whether the sampling clock signal makes appearance within a predetermined period of the internal clock signal to produce a signal representative of the result of the decision, and a control circuit having inputs supplied with the conditioning signal and the signal representative of said result for producing a trigger signal corresponding to the conditioning signal in dependence on the signal representative of the result of decision.

Abstract: A logic analyzer includes a plurality of data sampling channels which are operative in response to respective different clock signals independent of one another. Information of the sequence in time in which the sampled data are produced in the plurality of the sampling channels is stored in a memory for the purpose of display. To this end, each of the sampling channels is provided with a clock discriminating circuit having two inputs supplied with a common clock signal generated internally and a clock signal specific to the associated sampling channel. The outputs of all the clock discriminating circuits are stored in a memory whose contents thus indicate the sequence in time in which the data are sampled in the plurality of the sampling channels.