Abstract: A plurality of cells providing constituent elements for a semiconductor integrated circuit are provided in and on a major surface of a semiconductor substrate of a semiconductor integrated circuit chip. A plurality of wires are each provided between a cell and a cell to provide cell-to-cell wires. A plurality of dummy wires are connected to an internal power source terminal of a second power source potential which is different from a first power source terminal. A capacitance is created between the dummy wire and the semiconductor substrate to prevent a voltage fluctuation at the power source. The dummy wires are selectively cut off the internal power source terminal of the second potential to correct a wrong connection line or a signal delay time.

Abstract: A low-noise output buffer circuit of this invention comprises a P-channel MOSFET having a source connected to a power source potential, for outputting the power source potential according to a first input signal, an N-channel MOSFET having a source connected to a ground potential, for outputting the ground potential according to a second input signal, a bipolar transistor having a collector connected to the power source potential, an emitter connected to an output terminal and a base connected to the drain of the P-channel MOSFET, and a diode having a cathode connected to the drain of the N-channel MOSFET and an anode connected to the base of the NPN bipolar transistor.