Patents by Inventor Masayoshi Asano

Masayoshi Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8785274
    Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: July 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Katsuyoshi Matsuura, Masayoshi Asano, Hiroyuki Ogawa, Myounggoo Lee
  • Patent number: 8686499
    Abstract: A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaya Katayama, Masayoshi Asano
  • Patent number: 8530931
    Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masayoshi Asano, Junichi Mitani
  • Patent number: 8503234
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Patent number: 8400828
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Publication number: 20120195121
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Application
    Filed: March 30, 2012
    Publication date: August 2, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Publication number: 20120193711
    Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.
    Type: Application
    Filed: November 21, 2011
    Publication date: August 2, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masayoshi Asano, Junichi Mitani
  • Publication number: 20120119292
    Abstract: A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.
    Type: Application
    Filed: September 7, 2011
    Publication date: May 17, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaya Katayama, Masayoshi Asano
  • Publication number: 20110280072
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Application
    Filed: July 22, 2011
    Publication date: November 17, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Patent number: 8014198
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Patent number: 8012849
    Abstract: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masayoshi Asano, Yoshiyuki Suzuki
  • Patent number: 7928515
    Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masayoshi Asano, Yoshiyuki Suzuki, Tetsuya Ito, Hajime Wada
  • Publication number: 20100304539
    Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween.
    Type: Application
    Filed: May 24, 2010
    Publication date: December 2, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuyoshi Matsuura, Masayoshi Asano, Hiroyuki Ogawa, Myounggoo Lee
  • Publication number: 20100255648
    Abstract: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.
    Type: Application
    Filed: June 15, 2010
    Publication date: October 7, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masayoshi Asano, Yoshiyuki Suzuki
  • Patent number: 7772634
    Abstract: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: August 10, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masayoshi Asano, Yoshiyuki Suzuki
  • Patent number: 7723825
    Abstract: According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Taiji Ema, Masayoshi Asano, Toru Anezaki, Junichi Ariyoshi
  • Patent number: 7683452
    Abstract: An image sensor has a plurality of pixels each with a photoelectric conversion element and a detection transistor the threshold voltage of which fluctuates in accordance with electrical charge generated in the photoelectric conversion element. The image sensor includes a second conductivity type shield region and a first conductivity type photoelectric conversion region; a first conductivity type well region linked to the photoelectric conversion region; a ring-like gate electrode; a second conductivity type source region at the inside of the ring-like gate electrode; a second conductivity type drain region. The image sensor further includes a potential pocket region that is formed in the well region below the ring-like gate electrode and accumulates the electrical charge, wherein the width of the gate electrode is formed narrower in the part adjacent to the photoelectric conversion region than in other parts.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: March 23, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Narumi Ohkawa, Masayoshi Asano, Toshio Nomura
  • Publication number: 20090180320
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Application
    Filed: March 26, 2009
    Publication date: July 16, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Publication number: 20080315319
    Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 25, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masayoshi ASANO, Yoshiyuki SUZUKI, Tetsuya ITO, Hajime WADA
  • Publication number: 20080001258
    Abstract: According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.
    Type: Application
    Filed: October 30, 2006
    Publication date: January 3, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Taiji Ema, Masayoshi Asano, Toru Anezaki, Junichi Ariyoshi