Abstract: An electrode material includes an active material particle and a solid electrolyte particle. The solid electrolyte particle includes Li, M, and X, wherein M is at least one selected from the group consisting of metal elements excluding Li and metalloid elements, and X is at least one selected from the group consisting of F, Cl, Br, and I. The ratio R1 of the volume of the active material particle to the sum of the volume of the active material particle and the volume of the solid electrolyte particle is greater than or equal to 10% and less than 65% when expressed as percentage. The ratio R2 of the average particle diameter of the active material particle to the average particle diameter of the solid electrolyte particle is greater than or equal to 0.5 and less than or equal to 3.4.

Abstract: A vehicle-mounted relay device includes a hardware unit implementing functions of first to third layer of OSI model, and a software unit implementing functions of fourth and upper layers of OSI model. The hardware unit includes a first abnormality recording section in which an abnormal frame detected during data relay is recorded, and a first abnormality recording processing section storing, in response to detection of the abnormal frame, the abnormal frame in the first abnormality recording section. The software unit includes a second vehicle information recording section in which vehicle information sequentially transmitted from an end ECU is stored, and a first diagnostic recording processing section, which reads out the abnormal frame from the first abnormality recording section and reads out the vehicle information from the second vehicle information recording section, and stores the readout abnormal frame and vehicle information in a diagnostic information recording section as diagnostic information.

Abstract: An automatic valet parking system includes a vehicle, a parking server, and a map server including a database. The vehicle includes: an operation plan determination portion that determines whether the saver-side operation plan is false; a request generating portion that requests the map server to transmit the parkable region information when the server-side operation plan is false; a vehicle-side operation planning portion that generates, based on the parkable region information, a vehicle-side operation plan including a route for guiding the vehicle to the target position in the unmanageable region in response to receiving the parkable region information; and an automatic operation control portion that is configured to: perform the automatic operation control according to the server-side operation plan when the server-side operation plan is not false; and perform the automatic operation control according to the vehicle-side operation plan when the server-side operation plan is false.

Abstract: An automatic valet parking system includes a vehicle, a parking server, and a map server. The parking server includes a server-side operation planning portion that generates a server-side operation plan including a route for guiding the vehicle to a target position. The vehicle includes: an operation plan determination portion that determines whether the server-side operation plan is false; an automatic operation control portion that performs automatic operation control according to the server-side operation plan; and an information transmission portion that acquires vehicle-related information about the vehicle and to transmit the vehicle-related information to the parking server when the operation plan determination portion determines that the server-side operation plan is false.

Abstract: The present invention provides a compound having excellent histone acetyl transferase inhibitory activity against EP300 and/or CREBBP, or a pharmacologically acceptable salt thereof. The compound is represented by the following formula (1) or a pharmacologically acceptable salt thereof: wherein ring Q1, ring Q2, R1, R2, R3 and R4 respectively have the same meanings as defined in the specification.

Abstract: The present invention provides a compound having excellent histone acetyl transferase inhibitory activity against EP300 and/or CREBBP, or a pharmacologically acceptable salt thereof. The compound is represented by the following formula (1) or a pharmacologically acceptable salt thereof: wherein ring Q1, ring Q2, R1, R2, R3 and R4 respectively have the same meanings as defined in the specification.

Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween.

Abstract: A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.

Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.

Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.

Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween.

Abstract: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.