Patents by Inventor Masayoshi Danbata
Masayoshi Danbata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8558990Abstract: An exposure method includes the following processes. An autofocus scan process is performed to detect a defocused portion of a first resist film over a semiconductor wafer and to generate a detection signal that indicates the defocused portion detected. A first exposure scan process is performed while selectively blinding the first resist film, with reference to a detection signal related to the defocused portion detected.Type: GrantFiled: May 11, 2011Date of Patent: October 15, 2013Assignee: Elpida Memory, Inc.Inventors: Masayoshi Danbata, Hisanori Ueno
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Publication number: 20110279798Abstract: An exposure method includes the following processes. An autofocus scan process is performed to detect a defocused portion of a first resist film over a semiconductor wafer and to generate a detection signal that indicates the defocused portion detected. A first exposure scan process is performed while selectively blinding the first resist film, with reference to a detection signal related to the defocused portion detected.Type: ApplicationFiled: May 11, 2011Publication date: November 17, 2011Applicant: Elpida Memory, Inc.Inventors: Masayoshi Danbata, Hisanori Ueno
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Patent number: 7495457Abstract: In order to provide a semiconductor device evaluation method and a semiconductor device evaluation apparatus for correctly detecting an error position and providing a substrate for observing a cross section without difficulties, a transport unit of a SEM apparatus moves a substrate on a stage. A detection unit detects electric information of observed objects including an error position arranged on the substrate.Type: GrantFiled: March 4, 2008Date of Patent: February 24, 2009Assignee: Elpida Memory, Inc.Inventor: Masayoshi Danbata
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Publication number: 20080218193Abstract: In order to provide a semiconductor device evaluation method and a semiconductor device evaluation apparatus for correctly detecting an error position and providing a substrate for observing a cross section without difficulties, a transport unit of a SEM apparatus moves a substrate on a stage. A detection unit detects electric information of observed objects including an error position arranged on the substrate.Type: ApplicationFiled: March 4, 2008Publication date: September 11, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Masayoshi Danbata
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Publication number: 20070186960Abstract: There is provided a system capable of supplying pure water containing almost no dissolved gas and pure water containing dissolved gas without increasing the amount of pure water manufactured in a volume production semiconductor factory. In the present invention, pure water is supplied using a pure water supply system, which includes: a pure water manufacturing means for manufacturing pure water having a dissolved gas concentration of 0.4 ppm or lower; a first pure water supply means capable of supplying the pure water from the pure water manufacturing means; a dissolving means that is coupled to the pure water manufacturing means via a coupling portion and dissolves gas in the pure water transferred from the pure water manufacturing means via the coupling portion; and a second pure water supply means capable of supplying the pure water in which the gas has been dissolved by the dissolving means.Type: ApplicationFiled: February 8, 2007Publication date: August 16, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Masayoshi Danbata
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Publication number: 20070113778Abstract: A silicon ingot is manufactured by pulling a nitrogen doped silicon single crystal. The oxygen concentration in the crystal is controlled during the pulling, so as to maintain a relationship between the oxygen and nitrogen concentration in the ingot, corresponding to the formula Oi=C1?[C2×(Log Ni)], where C1 and C2 are first and second constants, and Oi is the oxygen concentration and Ni is the nitrogen concentration in the ingot. C1 and C2 will vary depending on the defect criteria. For example, for one criteria C1 may equal to 146.3×1017 and C2 may equal to 9×1017, and Ni may be within the range of approximately 3×1015 to approximately 3×1014 atoms/cm3, while for a stricter defect criteria C1 may equal 127×1017 and C2 may equal 8×1017, and Ni may be within the range proximately 1×1015 to approximately 1×1014 atoms/cm3.Type: ApplicationFiled: January 16, 2007Publication date: May 24, 2007Applicant: SUMCO TECHXIV CORPORATIONInventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouchirou Hayashida
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Patent number: 7147710Abstract: There is described a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method. A method of manufacturing an epitaxial silicon wafer having an ultra-thin epitaxial film, by means of forming an epitaxial film on a silicon wafer after having annealed the silicon wafer, includes the steps of: sufficiently smoothing COPs formed in the surface of the silicon wafer by means of appropriately setting annealing conditions according to an size of COPs in the vicinity of a surface of the silicon wafer; and forming an epitaxial film through epitaxial growth.Type: GrantFiled: November 18, 2002Date of Patent: December 12, 2006Assignee: Komatsu Denshi Kinzoku Kabushiki KaishaInventors: Kazuya Togashi, Masayoshi Danbata, Kuniaki Arai, Kaori Matsumoto
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Patent number: 6800132Abstract: A method for producing a silicon ingot through pulling up a silicon single crystal according to the Czochralski method, wherein the silicon single crystal is pulled up while being doped with nitrogen in such a condition as to form a part having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3. A silicon wafer having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3 which is suitable for being treated with heat in a non-oxidizing atmosphere is manufactured of an ingot produced by using the method. The method can be used for producing a silicon wafer being doped with nitrogen and having satisfactory characteristics for use in a semiconductor device.Type: GrantFiled: February 12, 2002Date of Patent: October 5, 2004Assignee: Komatsu Denshi Sinzoku KabushikiInventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouichirou Hayashida
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Publication number: 20040065250Abstract: An epitaxial silicon wafer which comprises a silicon wafer produced by a method characterized as comprising pulling up a silicon single crystal under a condition wherein when an oxygen concentration is 7×1017 atoms/cm3 a nitrogen concentration is about 3×1015 atoms/cm3 or less, and when an oxygen concentration is 1.6×1018 atoms/cm3 a nitrogen concentration is about 3×1014 atoms/cm3 or less, and, an epitaxial film formed on the wafer. The epitaxial film, being formed on such a wafer, has crystal defects, which are observed as LPD of 120 nm or more on the epitaxial film, in a range of 20 pieces/200-mm wafer or less. The epitaxial silicon wafer contains nitrogen atoms doped therein and also has satisfactory characteristics as that for use in a semiconductor device.Type: ApplicationFiled: October 3, 2003Publication date: April 8, 2004Applicant: Komatsu Denshi Kinzoku Kabushiki KaishaInventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouichirou Hayashida
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Publication number: 20030068502Abstract: There is described a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method. A method of manufacturing an epitaxial silicon wafer having an ultra-thin epitaxial film, by means of forming an epitaxial film on a silicon wafer after having annealed the silicon wafer, includes the steps of: sufficiently smoothing COPs formed in the surface of the silicon wafer by means of appropriately setting annealing conditions according to an size of COPs in the vicinity of a surface of the silicon wafer; and forming an epitaxial film through epitaxial growth.Type: ApplicationFiled: November 18, 2002Publication date: April 10, 2003Applicant: Komatsu Denshi Kinzoku Kabushiki KaishaInventors: Kazuya Togashi, Masayoshi Danbata, Kuniaki Arai, Kaori Matsumoto
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Patent number: 6217650Abstract: In an epitaxial-wafer fabricating process for epitaxially growing a silicon layer on the surface of a silicon wafer having the crystal orientation <100> or <111> and an inclination angle of 0°±1° in a reactive gas at a atmosphereicpressure, a growth temperature T is lower than a normal growth temperature by 50° C. to 100° C. during the process of epitaxial growth.Type: GrantFiled: June 15, 1999Date of Patent: April 17, 2001Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Takeshi Hirose, Hiroyuki Kawahara, Takeo Tamura, Masayoshi Danbata