Patents by Inventor Masayoshi Higashizono

Masayoshi Higashizono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5238873
    Abstract: A method for manufacturing a semiconductor device, comprising the steps of forming an oxide film selectively on the surface of a semiconductor substrate; forming a first polycrystalline silicon film on the whole surface and then forming a metallic silicide film on the surface of the first polycrystalline silicon film; patterning the first polycrystalline silicon film and the metallic silicide film except for the desired areas by a lithographic method; depositing polycrystalline silicon on the whole surface to thereby form a second polycrystalline silicon film and allow it to cover the patterned first polycrystalline silicon film and metallic silicide film; and performing oxidation in a state in which a boundary portion between the first polycrystalline silicon film and the metallic silicide film is not exposed to an oxidizing atmosphere by the presence of the second polycrystalline silicon film, to form an oxide film on the surface.
    Type: Grant
    Filed: October 2, 1991
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayoshi Higashizono, Yasunobu Kodaira, Katsuya Shino
  • Patent number: 5014106
    Abstract: A semiconductor device for use in a hybrid LSI circuit is disclosed which comprises MOSFETs and at least two bipolar transistor--all formed on the same semiconductor substrate. More specifically, p.sup.+ -type buried diffusion layers and p.sup.+ -type buried diffusion layers are formed on a P-type semiconductor substrate. An N-type epitaxial layer is formed on these buried layers. N-type well-regions and a P-type well-region are formed in the selected portions of the N-type epitaxial layer. A P-channel MOSFET and an N-channel MOSFET are formed in the N-type well-region and the P-type well-region, respectively. A first bipolar transistor is formed on the N-type epitaxial layer. A second bipolar transistor is formed on the N-type well-region which has an impurity concentration higher than that of the N-type epitaxial layer.
    Type: Grant
    Filed: March 7, 1990
    Date of Patent: May 7, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Maeda, Masayoshi Higashizono