Abstract: A semiconductor device has a wiring board having a wiring, a semiconductor chip that is mounted on the wiring board, and an electric conductor reference plane provided in the inside of the wiring board, in which in top view. The wiring includes a first region that overlaps the electric conductor reference plane and a second region that is the whole region except for the first region. A conductor chip is mounted above the second region.

Abstract: A semiconductor device includes an interposer, and a semiconductor chip mounted on the interposer. In a plan view, the interposer includes a first region overlapping the semiconductor chip, and a second region excluding the first region. The interposer includes at least one wiring formed astride the first region and the second region. The cross-sectional area of the wiring in the first region and the cross-sectional area of the wiring in the second region are different from each other.

Abstract: A semiconductor integrated circuit is provided with: a variable resistor section, a variable delay section and a data fetch section. The variable resistor section provides damping for a data signal inputted thereto to thereby generate a damped data signal. The damping resistance of the damping is variable. The variable delay section gives a variable delay to a clock signal to thereby generate a delayed clock signal. The data fetch section fetches data from the damped data signal in synchronization with the delayed clock signal.

Abstract: A semiconductor device has a wiring board having a wiring, a semiconductor chip that is mounted on the wiring board, and an electric conductor reference plane provided in the inside of the wiring board, in which in top view. The wiring includes a first region that overlaps the electric conductor reference plane and a second region that is the whole region except for the first region. A conductor chip is mounted above the second region.

Abstract: A semiconductor device includes an interposer, and a semiconductor chip mounted on the interposer. In a plan view, the interposer includes a first region overlapping the semiconductor chip, and a second region excluding the first region. The interposer includes at least one wiring formed astride the first region and the second region. The cross-sectional area of the wiring in the first region and the cross-sectional area of the wiring in the second region are different from each other.

Abstract: A boosting circuit for supplying a boosted voltage to an external capacitor, includes a plurality of capacitors, a charging section and a connection control section. The charging section charges each of the plurality of capacitors to a power supply voltage in a charging mode. The connection control section connects, in the boosting mode, the plurality of capacitors in series while a first one of the plurality of charged capacitors is biased by the power supply voltage such that the external capacitor is charged by the plurality of capacitors connected in series.

Abstract: The semiconductor device of the present invention with an IC chip provided on one side of a substrate, comprises a plurality of connection terminals, which are provided on the other side of the substrate, are electrically connected to the IC chip through electrical connecting devices, form a rectangular grid array, and are arranged in positions other than corners of the array.

Abstract: The semiconductor device of the present invention with an IC chip provided on one side of a substrate, comprises a plurality of connection terminals, which are provided on the other side of the substrate, are electrically connected to the IC chip through electrical connecting devices, form a rectangular grid array, and are arranged in positions other than corners of the array.

Abstract: A semiconductor memory apparatus including a current detecting circuit, an input signal generating circuit, a reference current detecting circuit, a reference input signal generating circuit and a differential amplifier circuit. The current detecting circuit detects a current flowing through a memory cell to output a detecting signal from an output section of the current detecting circuit. The input signal generating circuit generates a first differential input signal by amplifying the detecting signal to output from an output section of the input signal generating circuit. The reference current detecting circuit detects a current flowing through a reference cell to output a reference detecting signal from an output section of the reference current detecting circuit. The reference input signal generating circuit generates a second differential input signal by amplifying the reference detecting signal to output from an output section of the reference input signal generating circuit.

Abstract: In an erasing device or method for a storage unit, or a storage medium storing a program for erasing the storage unit, an output VS of a column decoder and a reference voltage VR are compared at a sense amplifier, while an erase operation is executed by taking out an electric charge of each cell in a memory cell array, after which the output of the sense amplifier is evaluated at a data determination circuit, and a signal DD is counted by a bit counter under the condition of VS<VR. As the entirety of addresses of an address signal ADD from an internal address increment circuit are finished, a signal FG rises. When a count number of a bit counter is above a predetermined number, an erasing routine is terminated, and thus it is possible to prevent the majority of the bits from falling into a state of depression.

Abstract: In a non-volatile semiconductor memory device, a memory cell array composed of a plurality of non-volatile memory cells is provided. Each word line is connected to a row of the memory cell array, and each bit line is connected to a column of the memory cell array. The memory cell array is divided into N blocks (N is an integer more than 1) in a row direction. A control signal generating section monitors erase operations to each of the N blocks to generate an erase operation history data for each of the N blocks and generates a control signal for each of the N blocks other than a selected block based on the erase operation history data for the corresponding block, when a write operation is performed to the selected block.

Abstract: Dummy memory cells are provided which have substantially the same structure as the main memory cells. A main sense amplifier is provided for reading out data from the main memory cells. A dummy sense amplifier is provided for reading out data from the dummy memory cells. A data latching circuit is provided for latching the data outputted from the main sense amplifier. Read out operations from the dummy memory cells are made at the same time as the read out operations from the main memory cells. The data latch circuit latches data outputted from the main sense amplifier by utilizing the timing when the dummy sense amplifier outputs data of the dummy memory cells.

Abstract: Disclosed is an electrically erasable and programmable non-volatile storage device, which has: an erase operation control means for outputting a first signal to write or erase data to or from a memory cell when receiving a write or erase operation signal; a write or erase pulse width control means which decides a write or erase pulse width according to the first signal and outputs a pulse; a write or erase pulse generating means which generates a write or erase pulse to be applied to the memory cell according to the pulse output from the write or erase pulse width control means; a verifying means which decides whether or not the memory cell to which the write or erase pulse is applied reaches a threshold voltage and which outputs the decision as a second signal to the write or erase operation control means; and a write or erase pulse width setting means which outputs a third signal to change the write or erase pulse width on the basis of the first signal and the second signal to the write or erase pulse width

Abstract: In a flash memory, each of substitution information circuits associated to a redundant memory cell array has an erase circuit for erasing the substitution information stored in memory cells in the substitution information circuit when the defectiveness of the corresponding memory cell in a main memory cell array is dissolved.

Abstract: The power supply circuit of the present invention comprises a first transfer circuit provided between a first power supply terminal and a supply voltage output terminal; a second transfer circuit provided between a second power supply terminal and said supply voltage output terminal; a first control circuit for making the first transfer circuit nonconductive at least when a first supply voltage is applied to the first power supply terminal, and a second supply voltage higher than the first supply voltage is applied to the second power supply terminal; and a second control circuit for making the second transfer circuit conductive only when said first supply voltage is applied to the first power supply terminal, and the second supply voltage is applied to the second power supply terminal.

Abstract: In a semiconductor memory device 100 including a power supply voltage decision circuit 101 for detecting whether or not the power supply voltage is higher than a predetermined level to produce an output signal LVD, an oscillator 102 which produces an oscillated signal .phi. as an output signal, an intended counter value altering circuit 103, and a binary counter circuit 104, a writing or erasing time interval is elongated by the output signal LVD, when the power supply voltage becomes lower than the predetermined level.

Abstract: When an electrically erasable and programmable read only memory device enters a programming mode of operation, write-in data bits are sequentially compared with read-out data bits stored in the memory cells associated with the write-in data bits to see whether or not the write-in data bits are consistent with the read-out data bits, and the programming is carried out in case of inconsistence between the write-in data bits and the read-out data bits; however, if all of the write-in data bits are consistent with the read-out data bits, the write-in data bits are never written into the memory cells so that write-in/erasing characteristics are free from aged deterioration.