Abstract: A data processor (1) has a central processing unit (3) and a memory controller (6) capable of controlling a memory (8) to be connected to an outside. The memory has a buffer capable of temporarily holding data within an address range corresponding to a predetermined bit number on a low order side of an address signal, and a burst operation for inputting/outputting data can be carried out by a data transfer between the buffer and the outside for an access request in which an access address is changed within the address range. When causing the memory to carry out the burst operation to give an access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects an access exceeding the address range. When causing the memory to carryout the burst access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects the access exceeding the address range.

Abstract: A data processor (1) has a central processing unit (3) and a memory controller (6) capable of controlling a memory (8) to be connected to an outside. The memory has a buffer capable of temporarily holding data within an address range corresponding to a predetermined bit number on a low order side of an address signal, and a burst operation for inputting/outputting data can be carried out by a data transfer between the buffer and the outside for an access request in which an access address is changed within the address range. When causing the memory to carry out the burst operation to give an access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects an access exceeding the address range. When causing the memory to carryout the burst access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects the access exceeding the address range.

Abstract: A data processor (1) has a central processing unit (3) and a memory controller (6) capable of controlling a memory (8) to be connected to an outside. The memory has a buffer capable of temporarily holding data within an address range corresponding to a predetermined bit number on a low order side of an address signal, and a burst operation for inputting/outputting data can be carried out by a data transfer between the buffer and the outside for an access request in which an access address is changed within the address range. When causing the memory to carry out the burst operation to give an access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects an access exceeding the address range. When causing the memory to carry out the burst access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects the access exceeding the address range.

Abstract: A data processor (1) has a central processing unit (3) and a memory controller (6) capable of controlling a memory (8) to be connected to an outside. The memory has a buffer capable of temporarily holding data within an address range corresponding to a predetermined bit number on a low order side of an address signal, and a burst operation for inputting/outputting data can be carried out by a data transfer between the buffer and the outside for an access request in which an access address is changed within the address range. When causing the memory to carry out the burst operation to give an access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects an access exceeding the address range. When causing the memory to carry out the burst access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects the access exceeding the address range.