Patents by Inventor Masayoshi Isomura

Masayoshi Isomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4413212
    Abstract: There is provided a digitized motor control apparatus which is capable of digitally effecting all the functions of the motor control apparatus except those involved in energy conversion.
    Type: Grant
    Filed: January 27, 1982
    Date of Patent: November 1, 1983
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Kiyokazu Okamoto, Masayoshi Isomura
  • Patent number: 4118776
    Abstract: With a microprogrammable computer of a numerically controlled machine, macroinstructions are executed in response to a first microprogram. The computer makes the machine carry out its inherent functions, such as interpolation, in response to a second microprogram. Flags may be used to switch sequential execution of the macroinstructions to repeated execution of a portion of the macroinstructions and sequential execution of microinstructions of the second microprogram.
    Type: Grant
    Filed: August 15, 1977
    Date of Patent: October 3, 1978
    Assignee: Nippon Electric Company, Ltd.
    Inventor: Masayoshi Isomura
  • Patent number: 4027292
    Abstract: A synchronous digital data processing system employing single-phase clock pulses comprises arithmetic and control units which are capable of completing an operation during one clock pulse period. The data processing system includes closed data paths wherein only one stage of a memory circuit capable of the same operation as a master/slave flip-flop is used as a data register in the arithmetic unit and as an address register in the control unit. In either case, during one cycle of a single-phase clock pulse, an input data is set in the memory circuit, and the output of the memory circuit is renewed in response to the input data. The output of the memory circuit is held until it is renewed in the following cycle.
    Type: Grant
    Filed: December 27, 1974
    Date of Patent: May 31, 1977
    Assignee: Nippon Electric Company, Limited
    Inventors: Kiyokazu Okamoto, Masayoshi Isomura, Atsuto Kobayashi