Abstract: The present invention discloses a register file in which a read access time is reduced, a data bus width is made expandable, more rapid decoding can be given at a time of data readout, and the whole logic unit is made higher in performance. For these purposes, in the register file of the invention, register arrays are classified into a plurality of banks, and a sense amplifier is provided for each of the banks. Further, the register file includes a decoder to select a word corresponding to a result of decoding of partial bits of a read address so as to read the word from the register array in each of the banks, a decoder to specify a bank corresponding to a result of decoding of remaining bits of the read address, and a multiplexer to select the word from the bank specified by the decoder so as to output the word to the read port.

Abstract: A static RAM is disclosed wherein a combination logic circuit can operate at a higher speed to improve the throughput and the load such as the number of gates and/or wiring lines connected to a data output line can be reduced. The static RAM comprises a RAM cell for storing data, a differential amplifier for amplifying a signal read out from the RAM cell, a level keeping circuit for keeping a level of a signal outputted from the differential amplifier, a first output line for outputting an output signal of a kept level from the level keeping circuit upon reading accessing to the static RAM as a static output, and a second output line for outputting a state of at least one of a positive phase bit line and an inverted phase bit line of the differential amplifier upon reading accessing to the static RAM as a dynamic output. The static RAM can be suitably used with an associative storage circuit represented by a tag RAM circuit of a cache memory system and like storage circuits.