Patents by Inventor Masayoshi Kosaki

Masayoshi Kosaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8420516
    Abstract: The present invention provides a method for producing an n-type Group III nitride semiconductor product having a high Si concentration and exhibiting favorable crystallinity. In the production method, specifically, an AlN buffer layer is formed on a sapphire substrate by MOCVD, and then a first layer (thickness: 2 ?m) is formed from undoped GaN on the buffer layer by MOCVD at 1,140° C. Subsequently, a second layer (thickness: 200 nm) is formed from SiO2 on the first layer by plasma CVD, and then the second layer is removed by use of BHF (buffered hydrofluoric acid). Next, a GaN layer (thickness: 50 nm) is grown, by MOCVD at 1,140° C., on the first layer exposed by removal of the second layer without supply of an n-type dopant gas. Thus, on the first layer is provided a third layer formed of n-type GaN doped with Si at a high concentration and exhibiting favorable crystallinity.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: April 16, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Kosaki, Hiroshi Miwa
  • Publication number: 20110306190
    Abstract: The present invention provides a method for producing an n-type Group III nitride semiconductor product having a high Si concentration and exhibiting favorable crystallinity. In the production method, specifically, an AlN buffer layer is formed on a sapphire substrate by MOCVD, and then a first layer (thickness: 2 ?m) is formed from undoped GaN on the buffer layer by MOCVD at 1,140° C. Subsequently, a second layer (thickness: 200 nm) is formed from SiO2 on the first layer by plasma CVD, and then the second layer is removed by use of BHF (buffered hydrofluoric acid). Next, a GaN layer (thickness: 50 nm) is grown, by MOCVD at 1,140° C., on the first layer exposed by removal of the second layer without supply of an n-type dopant gas. Thus, on the first layer is provided a third layer formed of n-type GaN doped with Si at a high concentration and exhibiting favorable crystallinity.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 15, 2011
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Masayoshi Kosaki, Hiroshi Miwa
  • Patent number: 7981744
    Abstract: A field-effect transistor which comprises a buffer layer and a barrier layer each of which is made of a Group III nitride compound semiconductor and has a channel at the interface inside of the buffer layer to the barrier layer, wherein the barrier layer has multiple-layer structure comprising an abruct interface providing layer which composes the lowest semiconductor layer in said barrier layer and whose composition varies rapidly at the interface of said buffer layer, and an electrode connection plane providing layer which constructs the uppermost semiconductor layer and whose upper surface is formed flat.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: July 19, 2011
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Kosaki, Koji Hirata, Masanobu Senda, Naoki Shibata
  • Patent number: 7750351
    Abstract: An epitaxial crystal for a field effect transistor which has a nitride-based III-V group semiconductor epitaxial crystal grown on a SiC single crystal base substrate having micropipes by use of an epitaxial growth method, wherein at least a part of the micropipes spreading from the SiC single crystal base substrate into the epitaxial crystal terminate between an active layer of the transistor and the SiC single crystal base substrate.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: July 6, 2010
    Assignees: Sumitomo Chemical Company, Limited, Toyoda Gosei Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroyuki Sazawa, Koji Hirata, Masayoshi Kosaki, Hajime Okumura
  • Publication number: 20090173969
    Abstract: A semiconductor device having an AlGaN—GaN heterojunction structure including an AlGaN layer and a GaN layer which device exhibits no changes over time in sheet resistance. As shown in FIG. 1, in a semiconductor device having an AlGaN—GaN heterojunction structure including an AlGaN layer 1 and a GaN layer 2, when the Al molar fraction of AlGaN (x %) and the thickness of the AlGaN layer (y nm) satisfy the relations: x+y<55, 25?x?40, and y?10, y is smaller than the critical thickness, whereby no cracks are generated in the AlGaN layer. Therefore, the invention provides a semiconductor device exhibiting virtually no changes over time in sheet resistance despite high Al molar fraction.
    Type: Application
    Filed: May 30, 2007
    Publication date: July 9, 2009
    Inventors: Junjiro Kikawa, Akira Suzuki, Masayoshi Kosaki, Koji Hirata
  • Patent number: 7554132
    Abstract: An electronic device includes a substrate; a single-crystalline first buffer layer, disposed on the substrate, containing a semiconductor represented by the formula AlxGa1?xN; a non-single-crystalline second buffer layer, disposed on the first buffer layer, containing a semiconductor represented by the formula AlyGa1?yN; and an undoped base layer, disposed on the second buffer layer, containing GaN, wherein 0<×?1 and 0?y?1. The first buffer layer is formed at a temperature of 1000° C. to 1200° C. The second buffer layer is formed at a temperature of 350° C. to 800° C. The substrate contains SiC. The second buffer layer has a thickness of 5 to 20 nm.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: June 30, 2009
    Assignee: Toyoda Gosei, Co., Ltd.
    Inventors: Masayoshi Kosaki, Koji Hirata
  • Publication number: 20090001384
    Abstract: Provided is an HFET exhibiting reduced buffer leakage current. The HFET of the present invention includes an SiC substrate, an AlN layer, a graded AlGaN layer, a GaN layer, an AlGaN layer (Al compositional proportion: 20%), a source electrode, a gate electrode, and a drain electrode, wherein the AlN layer, the graded AlGaN layer, the GaN layer, and the AlGaN (Al: 20%) layer are successively stacked on the substrate, and the electrodes are formed on the AlGaN (Al: 20%) layer so as to be separated from one another. In the graded AlGaN layer, the Al compositional proportion gradually decreases from 30% (at the side facing the AlN layer) to 5% (at the side facing the GaN layer). Provision of the graded AlGaN layer reduces strain between the AlN layer and the GaN layer. Therefore, the HFET exhibits reduced buffer leakage current.
    Type: Application
    Filed: June 25, 2008
    Publication date: January 1, 2009
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Masayoshi Kosaki, Yuhei Ikemoto, Takahiro Sonoyama, Hiroshi Miwa
  • Patent number: 7432538
    Abstract: A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The channel is formed near the interface between the channel layer and the carrier supply layer or depleted, the carrier supply layer has a band gap energy greater than that of the channel layer, and x in the formula AlxGa1-xN decreases monotonically with an increase in the distance from the interface. The channel layer may be crystalline of gallium nitride. The channel layer may be undoped. X of the formula AlxGa1-xN of the carrier supply layer is greater than or equal to 0.15 and less than or equal to 0.40 at the interface.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: October 7, 2008
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Kosaki, Koji Hirata
  • Publication number: 20070278532
    Abstract: A field-effect transistor which comprises a buffer layer and a barrier layer each of which is made of a Group III nitride compound semiconductor and has a channel at the interface inside of the buffer layer to the barrier layer, wherein the barrier layer has multiple-layer structure comprising an abruct interface providing layer which composes the lowest semiconductor layer in said barrier layer and whose composition varies rapidly at the interface of said buffer layer, and an electrode connection plane providing layer which constructs the uppermost semiconductor layer and whose upper surface is formed flat.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 6, 2007
    Inventors: Masayoshi Kosaki, Koji Hirata, Masanobu Senda, Naoki Shibata
  • Publication number: 20070069239
    Abstract: An electronic device includes a substrate; a single-crystalline first buffer layer, disposed on the substrate, containing a semiconductor represented by the formula AlxGa1-xN; a non-single-crystalline second buffer layer, disposed on the first buffer layer, containing a semiconductor represented by the formula AlyGa1-yN; and an undoped base layer, disposed on the second buffer layer, containing GaN, wherein 0<×?1 and 0?y?1. The first buffer layer is formed at a temperature of 1000° C. to 1200° C. The second buffer layer is formed at a temperature of 350° C. to 800° C. The substrate contains SiC. The second buffer layer has a thickness of 5 to 20 nm.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 29, 2007
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Masayoshi Kosaki, Koji Hirata
  • Publication number: 20070069253
    Abstract: An epitaxial crystal for a field effect transistor which has a nitride-based III-V group semiconductor epitaxial crystal grown on a SiC single crystal base substrate having micropipes by use of an epitaxial growth method, wherein at least a part of the micropipes spreading from the SiC single crystal base substrate into the epitaxial crystal terminate between an active layer of the transistor and the SiC single crystal base substrate.
    Type: Application
    Filed: March 23, 2006
    Publication date: March 29, 2007
    Applicants: Sumitomo Chemical Company, Limited, Toyoda Gosei Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroyuki Sazawa, Koji Hirata, Masayoshi Kosaki, Hajime Okumura
  • Publication number: 20070063220
    Abstract: A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The channel is formed near the interface between the channel layer and the carrier supply layer or depleted, the carrier supply layer has a band gap energy greater than that of the channel layer, and x in the formula AlxGa1-xN decreases monotonically with an increase in the distance from the interface. The channel layer may be crystalline of gallium nitride. The channel layer may be undoped. X of the formula AlxGa1-xN of the carrier supply layer is greater than or equal to 0.15 and less than or equal to 0.40 at the interface.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 22, 2007
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Masayoshi Kosaki, Koji Hirata