Patents by Inventor Masayoshi Kusumoto

Masayoshi Kusumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097132
    Abstract: An electrode material includes an active material particle and a solid electrolyte particle. The solid electrolyte particle includes Li, M, and X, wherein M is at least one selected from the group consisting of metal elements excluding Li and metalloid elements, and X is at least one selected from the group consisting of F, Cl, Br, and I. The ratio R1 of the volume of the active material particle to the sum of the volume of the active material particle and the volume of the solid electrolyte particle is greater than or equal to 10% and less than 65% when expressed as percentage. The ratio R2 of the average particle diameter of the active material particle to the average particle diameter of the solid electrolyte particle is greater than or equal to 0.5 and less than or equal to 3.4.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: MASAYOSHI UEMATSU, AKIHIKO SAGARA, HIROSHI ASANO, SHOHEI KUSUMOTO, TOMOKATSU WADA
  • Patent number: 7787479
    Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: August 31, 2010
    Assignees: Fujitsu Ten Limited, Fujitsu Limited
    Inventors: Tomohiro Matsuo, Tsuyoshi Takatori, Kaoru Noumi, Susumu Nishihashi, Tomohide Kasame, Yukio Ishikawa, Junji Takahashi, Yasuyuki Umezaki, Akiko Furuya, Nobuaki Kawasoe, Naoto Shimoji, Masayoshi Kusumoto
  • Patent number: 7174435
    Abstract: First and second latch circuits store “0” and “1”, respectively, by reset. An output signal from the first latch circuit is input to the second latch circuit. Register setting data is input to the first latch circuit via a first gate that allows an input signal to pass through when the output signal from the second latch circuit is “1”, and outputs “0” when the output signal from the second latch circuit is “0”. A write signal is supplied to a memory via a second gate that allows the input signal to pass through only when the output signal from the first latch circuit is “1”. When the register setting data indicates “0”, the output signals from both the first and the second latch circuits become “0”, and until being reset, the write error protect state is maintained.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: February 6, 2007
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Yoshida, Yoshihiko Koike, Masayoshi Kusumoto
  • Publication number: 20060271694
    Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 30, 2006
    Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED
    Inventors: Tomohiro Matsuo, Tsuyoshi Takatori, Kaoru Noumi, Susumu Nishihashi, Tomohide Kasame, Yukio Ishikawa, Junji Takahashi, Yasuyuki Umezaki, Akiko Furuya, Nobuaki Kawasoe, Naoto Shimoji, Masayoshi Kusumoto
  • Publication number: 20040153906
    Abstract: An interrupt vector is stored in a bank B of a dual operation flash memory, and an alternate interrupt vector corresponding to the interrupt vector is stored in a bank A. During rewrite processing of the bank B, if a CPU accesses the interrupt vector, an interrupt vector address conversion circuit converts the address of the interrupt vector to the address of the alternate interrupt vector, to access the memory. As a result, the interrupt vector data can be obtained to start the interrupt processing.
    Type: Application
    Filed: November 19, 2003
    Publication date: August 5, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masayoshi Kusumoto, Tetsuya Yoshida
  • Publication number: 20040139289
    Abstract: First and second latch circuits store “0” and “1”, respectively, by reset. An output signal from the first latch circuit is input to the second latch circuit. Register setting data is input to the first latch circuit via a first gate that allows an input signal to pass through when the output signal from the second latch circuit is “1”, and outputs “0” when the output signal from the second latch circuit is “0”. A write signal is supplied to a memory via a second gate that allows the input signal to pass through only when the output signal from the first latch circuit is “1”. When the register setting data indicates “0”, the output signals from both the first and the second latch circuits become “0”, and until being reset, the write error protect state is maintained.
    Type: Application
    Filed: November 19, 2003
    Publication date: July 15, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuya Yoshida, Yoshihiko Koike, Masayoshi Kusumoto