Abstract: According to one embodiment, there is provided a host controller, which samples reception data in a VDS mode and an FDS mode, includes a VDS phase register which holds a phase shift amount in the VDS mode, an FDS phase register which holds a phase shift amount in the FDS mode, a mode setting unit configured to indicate in which of the VDS mode and the FDS mode data is sampled, a sampling position setting unit which selects the phase shift amount set in one of the VDS and the FDS phase register in accordance with a setting value of the mode setting unit, and provides the selected phase shift amount as a sampling position, and a clock phase shift unit which shifts a phase of an input clock signal in accordance with the shift amount, and provides the shifted input clock signal as a sampling clock.

Abstract: One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

Abstract: According to one embodiment, there is provided a host controller, which samples reception data in a VDS mode and an FDS mode, includes a VDS phase register which holds a phase shift amount in the VDS mode, an FDS phase register which holds a phase shift amount in the FDS mode, a mode setting unit configured to indicate in which of the VDS mode and the FDS mode data is sampled, a sampling position setting unit which selects the phase shift amount set in one of the VDS and the FDS phase register in accordance with a setting value of the mode setting unit, and provides the selected phase shift amount as a sampling position, and a clock phase shift unit which shifts a phase of an input clock signal in accordance with the shift amount, and provides the shifted input clock signal as a sampling clock.

Abstract: According to one embodiment, there is provided a host controller. The host controller includes a plurality of data input sections and a controller. The plurality of data input sections is configured to repeat an operation of acquiring a plurality of values by sampling a content of read data and additional information accompanying the content with a plurality of clocks of different phases. The controller is configured to adjust phases of the clocks based on the plurality of values acquired by the data input sections.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: A recording medium control element includes: an input/output module configured to input/output a command and data to/from a recording medium; a first control module configured to control the input/output of the command and data performed by the input/output module; a buffer holding the data input/output to/from the input/output module; a second control module configured to control writing and reading data to/from the buffer; a clock generating module configured to generate a first clock signal and a second clock signal whose frequency is lower than a maximum operating frequency of the recording medium; and a signal supply module configured to supply the first clock signal to the recording medium and the input/output module, and supplying the second clock signal to the first and second control modules.

Abstract: An electronic program table processing apparatus can obtain the number of receivable channels M and the standard number of channels N displayable on one screen. When EPG display data is generated, the apparatus examines whether or not the number M is smaller than the number N. If so, the apparatus generates the EPG to display the program information for M channels on one screen. If not, the apparatus generates the EPG to display the program information for N channels on one screen.

Abstract: A video recording apparatus, by comparing the preselected video recording duration with a preset reference video recording duration, assumes a video recording end time as an end time of a broadcast program next to the broadcast program for which the start of video recording is instructed in case the preselected video recording duration is shorter than the preset reference video recording duration, and assumes the video recording end time as the end time of the broadcast program for which the start of video recording is instructed in case that the preselected video recording duration is longer than the preset reference video recording duration.

Abstract: An information recording and reproducing apparatus with a ring buffer, in which user can know a state of the ring buffer in a real-time manner and a monitoring method of the ring buffer. A ring buffer monitor image signal is generated which indicates an image showing a relative positional relation of a current recording position and a current reproducing position in the ring buffer.

Abstract: A program information acquisition apparatus includes a program information acquisition unit, a program information accumulation unit, and a program information acquisition determining unit. In this configuration, a start of an acquisition operation by the program information acquisition unit is determined based on an information accumulation status of the program information accumulation unit. Thus, program information distributed from a desired reception target can be accumulated as the latest information as much as possible. Since unneeded program information is not acquired, program information acquisition with high energy saving effects is made possible.

Abstract: An electronic program table processing apparatus can obtain the number of receivable channels M and the standard number of channels N displayable on one screen. When EPG display data is generated, the apparatus examines whether or not the number M is smaller than the number N. If so, the apparatus generates the EPG to display the program information for M channels on one screen. If not, the apparatus generates the EPG to display the program information for N channels on one screen.

Abstract: An image display apparatus is provided with: a display device for displaying an image with a resolution of 1280×768; and an image processing device for making graphic video information for displaying a GUI, so as not to exceed the resolution of 1280×768 and according to a difference in resolution of primitive video information with a resolution of 1920×1080, and for combining the made graphic video information with the primitive video information. The display device extracts the graphic video information from the primitive video information, to thereby display the GUI based on the extracted graphic video information.

Abstract: Disclosed is an apparatus for recording and reproducing information and an information reproducing method in which the reproducing operation can be restarted from a position where reproduction was interrupted. The restart is possible for all of information contents recorded on a recording medium and without the need of troublesome operations. For this purpose, reproduction history information representing a reproduction history of each of the information contents recorded on the recording medium is stored in a management memory.

Abstract: Disclosed is an apparatus for recording and reproducing information and an information reproducing method in which the reproducing operation can be restarted from a position where reproduction was interrupted. The restart is possible for all of information contents recorded on a recording medium and without the need of troublesome operations. For this purpose, reproduction history information representing a reproduction history of each of the information contents recorded on the recording medium is stored in a management memory.

Abstract: A coordinate position detecting method uses a plurality of light emitting elements and a plurality of light receiving elements located on mutually opposite sides, all the elements being arranged at a predetermined interval in horizontal and vertical directions, with each pair of mutually opposed light emitting element and light receiving element forming a light beam path, such that the coordinate position of a light blocking object can be detected once the light beam path is blocked. The method comprises: storing N previous coordinate datas obtained when detecting a movement of the light blocking ojecte, using n (1≦n≦N) coordinate datas of the N previous coordinate datas to calculate a coordinate position of the light blocking object; and changing the number of the coordinate datas for use in calculating the coordinate position, in accordance with a speed of the movment of the light blocking object.

Abstract: A hard disc recorder searches some pieces of information that match a search condition from a plurality of pieces of information recorded on a recording medium. The hard disc recorder then prepares playback order information to successively play the searched pieces of information in a desired order. A new name is assigned to the searched pieces of information on the basis of the search condition.