Patents by Inventor Masayoshi Shimoda

Masayoshi Shimoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230238299
    Abstract: A semiconductor device includes a semiconductor chip, a bonding member, and a planar laminated substrate having the semiconductor chip bonded to a front surface thereof via the bonding member. The laminated substrate includes a planar ceramic board, a high-potential metal layer, a low-potential metal layer, an intermediate layer. The planar ceramic board contains a plurality of ceramic particles. The high-potential metal layer contains copper and is bonded to a first main surface of the ceramic board. The low-potential metal layer contains copper, is bonded to a second main surface of the ceramic board, and has a potential lower than a potential of the first main surface of the high-potential metal layer. The intermediate layer is provided between the second main surface and the low-potential metal layer and includes a first oxide that contains at least either magnesium or manganese.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Seiichi TAKAHASHI, Masayoshi SHIMODA, Makoto ISOZAKI
  • Patent number: 10189119
    Abstract: An object of the invention is to provide a lead-free solder for die bonding having a high heat resistance temperature and an improved wetting property. Provided are a solder alloy for die bonding which contains 0.05% by mass to 3.0% by mass of antimony and the remainder consisting of bismuth and inevitable impurities, and a solder alloy for die bonding which contains 0.01% by mass to 2.0% by mass of germanium and the remainder consisting of bismuth and inevitable impurities.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: January 29, 2019
    Assignees: Nihon Handa Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Takeshi Asagi, Susumu Mitani, Hirohiko Watanabe, Masayoshi Shimoda
  • Publication number: 20150258637
    Abstract: An object of the invention is to provide a lead-free solder for die bonding having a high heat resistance temperature and an improved wetting property. Provided are a solder alloy for die bonding which contains 0.05% by mass to 3.0% by mass of antimony and the remainder consisting of bismuth and inevitable impurities, and a solder alloy for die bonding which contains 0.01% by mass to 2.0% by mass of germanium and the remainder consisting of bismuth and inevitable impurities.
    Type: Application
    Filed: January 21, 2014
    Publication date: September 17, 2015
    Applicants: Nihon Handa Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Takeshi Asagi, Susumu Mitani, Hirohiko Watanabe, Masayoshi Shimoda
  • Patent number: 7670879
    Abstract: The present invention provides a manufacturing method of a semiconductor module which enables the joining at a low temperature within a short time and can obtain more reliable joining portions by performing the joining without using a solder joining medium.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: March 2, 2010
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Kozo Fujimoto, Hirohiko Watanabe, Kazutaka Ikemi, Keiichi Matsumura, Masayoshi Shimoda, Katsumi Taniguchi, Tomoaki Goto
  • Publication number: 20070197017
    Abstract: The present invention provides a manufacturing method of a semiconductor module which enables the joining at a low temperature within a short time and can obtain more reliable joining portions by performing the joining without using a solder joining medium.
    Type: Application
    Filed: March 2, 2004
    Publication date: August 23, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Kozo Fujimoto, Hirohiko Watanabe, Kazutaka Ikemi, Keiichi Matsumura, Masayoshi Shimoda, Katsumi Taniguchi, Tomoaki Goto
  • Publication number: 20070152025
    Abstract: The present invention provides an electronic part mounting method which enables joining of electrodes at a low temperature and within a short time, can obtain the high reliability and, further, enables joining at a fine pitch. In an electronic part mounting method which joins circuit electrodes which are formed over a circuit board and die electrodes which are formed over the electronic parts thus mounting the electronic parts on the circuit board, a low-melting-point metal layer is preliminarily formed over the circuit electrode and/or the die electrode and, thereafter, the circuit electrode and the die electrode are arranged to face each other and are heated and pressurized for melting low-melting-point metal thus diffusing the low-melting-point metal into the circuit electrode and the die electrode by solid-liquid diffusion.
    Type: Application
    Filed: March 2, 2004
    Publication date: July 5, 2007
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Kozo Fujimoto, Kazutaka Ikemi, Hirohiko Watanabe, Keiichi Matsumura, Masayoshi Shimoda, Katsumi Taniguchi, Tomoaki Goto