Abstract: A solid-state imaging device includes a pixel part, a reading part for reading a pixel signal from the pixel part and a response data generating part including a fuzzy extractor. The response data generating part generates response data including a unique key in association with at least one selected from among variation information of pixels and variation information of the reading part. The response data generating part generates, when regenerating a key, a unique key using helper data acquired in generation of an initial key, variation information acquired in the regeneration of the key, and reliability information determined based on the variation information acquired in the regeneration of the key.

Abstract: A fuzzy extractor includes an initial key generating part including a true random number generator, and a key regenerating part. The true random number generator generates a true random number using a read-out signal read from the reading part or a pixel signal read from the pixels of the pixel part in a true random number generation mode. The initial key generating part generates helper data and an initial key based on the true random number generated by the true random number generator and variation information acquired as a response when the initial key is generated. The key regenerating part generates, when a key is regenerated, a unique key based on helper data acquired when the initial key is generated and variation information acquired as a response including an error when the key is regenerated.

Abstract: A solid-state imaging device includes a pixel part, a reading part for reading a pixel signal from the pixel part and a response data generating part including a fuzzy extractor. The response data generating part generates response data including a unique key in association with at least one selected from among variation information of pixels and variation information of the reading part. The response data generating part generates, when regenerating a key, a unique key using helper data acquired in generation of an initial key, variation information acquired in the regeneration of the key, and reliability information determined based on the variation information acquired in the regeneration of the key.

Abstract: A fuzzy extractor includes an initial key generating part including a true random number generator, and a key regenerating part. The true random number generator generates a true random number using a read-out signal read from the reading part or a pixel signal read from the pixels of the pixel part in a true random number generation mode. The initial key generating part generates helper data and an initial key based on the true random number generated by the true random number generator and variation information acquired as a response when the initial key is generated. The key regenerating part generates, when a key is regenerated, a unique key based on helper data acquired when the initial key is generated and variation information acquired as a response including an error when the key is regenerated.

Abstract: A solid-state imaging device having a pixel portion in which a plurality of pixels each including a photodiode are arranged in rows and columns, a reading part for reading pixel signals from the pixel portion, and a key generation part which generates a unique key by using, as the key generation-use data, at least one of fluctuation information of pixels and fluctuation information of the reading part, wherein the key generation part includes a tamper resistance enhancement processing part for processing the key generation-use data to enhance the tamper resistance making it difficult to break the unique key as tamper resistance enhancement processing. Due to this, it is possible to generate a unique key having a high confidentiality. Further, it is possible to improve reproducibility and uniqueness of the unique ID, is possible to secure a high tamper resistance of the unique key, and consequently is possible to reliably prevent tampering and forgery of an image.

Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Abstract: A solid-state imaging device having a pixel portion in which a plurality of pixels each including a photodiode are arranged in rows and columns, a reading part for reading pixel signals from the pixel portion, and a key generation part which generates a unique key by using, as the key generation-use data, at least one of fluctuation information of pixels and fluctuation information of the reading part, wherein the key generation part includes a tamper resistance enhancement processing part for processing the key generation-use data to enhance the tamper resistance making it difficult to break the unique key as tamper resistance enhancement processing. Due to this, it is possible to generate a unique key having a high confidentiality. Further, it is possible to improve reproducibility and uniqueness of the unique ID, is possible to secure a high tamper resistance of the unique key, and consequently is possible to reliably prevent tampering and forgery of an image.

Abstract: A solid-state imaging device having a pixel portion in which a plurality of pixels each including a photodiode are arranged in rows and columns, a reading part for reading pixel signals from the pixel portion, and a key generation part which generates a unique key by using, as the key generation-use data, at least one of fluctuation information of pixels and fluctuation information of the reading part, wherein the key generation part includes a tamper resistance enhancement processing part for processing the key generation-use data to enhance the tamper resistance making it difficult to break the unique key as tamper resistance enhancement processing. Due to this, a unique key having a high confidentiality can be generated. Further, reproducibility and uniqueness of the unique ID can be improved to secure a high tamper resistance of the unique key, and tampering and forgery of an image can be reliably prevented.

Abstract: A solid-state imaging device having a pixel portion in which a plurality of pixels each including a photodiode are arranged in rows and columns, a reading part for reading pixel signals from the pixel portion, and a key generation part which generates a unique key by using, as the key generation-use data, at least one of fluctuation information of pixels and fluctuation information of the reading part, wherein the key generation part includes a tamper resistance enhancement processing part for processing the key generation-use data to enhance the tamper resistance making it difficult to break the unique key as tamper resistance enhancement processing. Due to this, a unique key having a high confidentiality can be generated. Further, reproducibility and uniqueness of the unique ID can be improved to secure a high tamper resistance of the unique key, and tampering and forgery of an image can be reliably prevented.

Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Abstract: A gate structure (4), an LDD region (6) and a sidewall (7) are provided in this order. Arsenic ions (8) are thereafter implanted into the upper surface of a silicon substrate (1) by tilted implantation. The next step is annealing for forming an MDD region (9) in the upper surface of the silicon substrate (1). The MDD region (9) and the gate structure (4) do not overlap one another in plan view. Further, the MDD region (9) formed into a depth shallower than that of the LDD region (6) is higher in concentration than the LDD region (6). Thereafter a source/drain region (11) higher in concentration than the MDD region (9) is provided by vertical implantation into a depth greater than that of the LDD region (6).

Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.

Abstract: A semiconductor device having a reduced overlap capacity between a gate electrode and extensions. Specifically, a stacked structure made up of a polysilicon film, tungsten silicide film, and silicon nitride film is partially formed in first and second regions of a silicon substrate, respectively. Sidewall oxide films are formed on side surfaces of the polysilicon films in the first and second regions, respectively. A width of the sidewall of the first structure is smaller than a width of the sidewall of the second structure such that an overlap amount between a second conductive layer and a second impurity region is smaller than an overlap amount between a first conductive layer and a first impurity region.

Abstract: A gate structure (4), an LDD region (6) and a sidewall (7) are provided in this order. Arsenic ions (8) are thereafter implanted into the upper surface of a silicon substrate (1) by tilted implantation. The next step is annealing for forming an MDD region (9) in the upper surface of the silicon substrate (1). The MDD region (9) and the gate structure (4) do not overlap one another in plan view. Further, the MDD region (9) formed into a depth shallower than that of the LDD region (6) is higher in concentration than the LDD region (6). Thereafter a source/drain region (11) higher in concentration than the MDD region (9) is provided by vertical implantation into a depth greater than that of the LDD region (6).

Abstract: A semiconductor device with a polycide interconnection including a refractory metal silicide film improved in adherence with an interlayer insulation film, and a method of fabricating such a semiconductor device are provided. The local impurity concentration of a tungsten silicide film in the proximity of the interface between an interlayer oxide film and the tungsten silicide film is set to 5×1019 atms/cm3-2×1022 atms/cm3.

Abstract: A semiconductor device—which includes surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film—and a manufacturing method therefor. A voltage is applied between an electrode connected to a gate electrode and an electrode connected to an N+ region formed in an n-well, and electrons are implanted into the gate electrode at high energy from a substrate, thereby producing fixed negative electric charges in a gate oxide film within an range of 1E11 cm−2 to 1E14 cm−2. An appropriate value for Vth is obtained in the surface channel MOSFET. Therefore, there are solved problems associated with a dual gate structure; namely, a complicated process flow, etch residues or excessive etching due to a difference in etch rate between n-type polycrystalline silicon and p-type polycrystalline silicon, and the deterioration of a gate oxide film due to penetration of boron ions.

Abstract: A gate electrode (GE1) includes a polysilicon layer (4C), silicon oxide films (reoxidation films) 14, a metal layer (50C), and silicide films (15). The polysilicon layer (4C) is formed on a main surface (3BS) of a gate insulating film (3B), and the silicon oxide films (14) are formed on the side walls (4CW) of the polysilicon layer (4C). The metal layer (50C) is formed in contact with the main surface (4CS1) of the polysilicon layer (4C) on the opposite side to the gate insulating film (3B). The silicide films (15) are formed on the side walls (50CW) of the metal layer (50C) (which are composed of side walls (51CW and 52CW) of first and second metal layers (51 and 52)). After the silicide films (15) are formed, the metal layer (50C) is protected by the silicide films (15). This structure provides an MOS transistor having a polymetal gate in which oxidation of the metal layer is prevented to realize lower resistivity.

Abstract: A method of manufacturing a semiconductor device. The method includes forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a first conductive layer on the gate insulating film, selectively forming a second conductive layer on the first conductive layer, and selectively imparting an insulating property to the first conductive layer by using the second conductive layer as a mask, to obtain an insulating layer. The method also includes forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left when the first conductive layer was imparted the insulating property.

Abstract: A semiconductor device—which includes surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film—and a manufacturing method therefor. A voltage is applied between an electrode connected to a gate electrode and an electrode connected to an N+ region formed in an n-well, and electrons are implanted into the gate electrode at high energy from a substrate, thereby producing fixed negative electric charges in a gate oxide film within an range of 1E11 cm−2 to 1E14 cm−2. An appropriate value for Vth is obtained in the surface channel MOSFET. Therefore, there are solved problems associated with a dual gate structure; namely, a complicated process flow, etch residues or excessive etching due to a difference in etch rate between n-type polycrystalline silicon and p-type polycrystalline silicon, and the deterioration of a gate oxide film due to penetration of boron ions.

Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.