Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.

Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.

Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.

Abstract: A system-on-chip (SoC) application-specific integrated circuit (ASIC) includes a processor, a finite state machine (FSM), and a security mechanism. The processor exposes debugging ports. The FSM permits permit instructions to be externally input to the debugging ports and data to be externally output from the debugging ports. The security mechanism prevents access to at least a subset of the debugging ports unless a security code externally input via a security interface of the security mechanism matches a predetermined internally stored security code. Additionally or alternatively, the security mechanism prevents at least a subset of the instructions from being processed unless a security code externally input via a security code instruction asserted on the debugging ports matches the predetermined internally stored security code.

Abstract: A microcomputer, a method for protecting memory and a method for performing debugging is provided including a TAP controller and instruction decoder for monitoring an external input for a processor, internal registers and comparators for determining whether or not the destination address of an access by the processor to ROM and SRAM is within a predetermined protected area, and internal registers and multiplexers as access control means. If a control instruction for the processor has been detected and an execution of an access from the processor to the protected area has been detected, the destination address of the access is replaced with addresses of a ROM and SRAM of an additional circuitry block that have been prepared by developers.

Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.

Abstract: The System on a Chip (SoC) according to the present invention provides debugging by reading or rewriting the contents of an arbitrary register within an SoC by a level-sensitive scan design (LSSD) scan test, and includes a scan chain for scan tests that connects a plurality of latch circuits in chain form and a debug circuit for, while performing a scan test on the scan chain, specifying a specific latch circuit constituting the scan chain and reading data from the latch circuit. The scan chain gives output back to the input of the first latch circuit, thus forming a feedback loop. There exist a plurality of such scan chains, each consisting of the same number of latch circuits, including latch circuits for performing a scan test and dummy latch circuits for making the number of latch circuits constituting the scan chain identical among all of the scan chains.

Abstract: A microcomputer, a method for protecting memory and a method for performing debugging is provided including a TAP controller and instruction decoder for monitoring an external input for a processor, internal registers and comparators for determining whether or not the destination address of an access by the processor to ROM and SRAM is within a predetermined protected area, and internal registers and multiplexers as access control means. If a control instruction for the processor has been detected and an execution of an access from the processor to the protected area has been detected, the destination address of the access is replaced with addresses of a ROM and SRAM of an additional circuitry block that have been prepared by developers.

Abstract: A computer system has a central processing unit (“CPU”) and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal (“IRDY”), a device select signal (“DEVSEL”) and a target ready signal (“TRDY”). First and second direct memory access devices (“DMA”) are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.

Abstract: A computer system has a central processing unit ("CPU") and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal ("IRDY"), a device select signal ("DEVSEL"), and a target ready signal ("TRDY"). First and second direct memory access devices ("DMA") are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.