Abstract: Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure.

Abstract: Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure.

Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.

Abstract: A clock input/output device has three-state inverters Iv1 to Iv3 and an inverter Iv4, which cooperate to make equal the on-state resistance through a supply-voltage-side (VDD-side) transistor and the on-state resistance through a ground-voltage-side (0-side) transistor so as to make equal to VDD/2 the threshold voltage with reference to which the clock input/output device evaluates the input thereto to determine whether or not to change the state of the output thereof.

Abstract: A comparator has: an offset setting portion adapted to set an offset voltage; an offset subtracting portion adapted to subtract the offset voltage from a non-inverting input voltage; and a comparing portion adapted to shift the output logic level thereof according to which of the output voltage of the offset subtracting portion and an inverting input voltage is higher.

Abstract: A semiconductor integrated circuit includes an oscillation circuit outputting an oscillation signal, and a switch circuit switching whether the oscillation signal received from the oscillation circuit is to be output to the outside or not.

Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.

Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Abstract: A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.

Abstract: A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.

Abstract: In generating a frequency-modulated clock, a first frequency modulation (FM) signal having frequency fm1 is frequency-modulated by a second FM signal having a second frequency fm2, generating a clock modulation signal fm0. The clock generation signal fm0 is used to frequency-modulate the system clock CLK by the clock modulation signal fm0. Thus, the spectrum of the clock is doubly dispersed by the first and the second FM frequencies. As a result, peak levels at the fundamental and higher harmonic frequencies are reduced as compared with conventional clock generation device.

Abstract: A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over the respective PLL circuit stages to attain the predetermined ratio, with the first PLL circuit stage receiving the first clock and the last PLL circuit stage outputting the second clock. The frequency division ratios distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.

Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the SIN ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Abstract: In generating a frequency-modulated clock, a first frequency modulation (FM) signal having frequency fm1 is frequency-modulated by a second FM signal having a second frequency fm2, generating a clock modulation signal fm0. The clock generation signal fm0 is used to frequency-modulate the system clock CLK by the clock modulation signal fm0. Thus, the spectrum of the clock is doubly dispersed by the first and the second FM frequencies. As a result, peak levels at the fundamental and higher harmonic frequencies are reduced as compared with conventional clock generation device.

Abstract: A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock. The frequency division ratios are distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.

Abstract: A constant voltage output device has a field-effect transistor and a comparator. Between the output electrode of the field-effect transistor and ground, a first resistor, a second resistor, and a first diode are connected in series. Moreover, between the output electrode of the field-effect transistor and ground, a third resistor and a second diode are connected in series. The comparator compares the voltage at the node between the first and second resistors with the voltage at the node between the third resistor and the second diode, and feeds the comparison result to the gate of the field-effect transistor. At an output terminal appears a desired voltage that is determined by the ratio between the current capacities of the first and second diodes and by the ratio between the resistances of the first and second resistors.