Patents by Inventor Masayuki Aoike

Masayuki Aoike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220199548
    Abstract: A semiconductor device includes first and second members. In the first member, a first electronic circuit including a semiconductor element is formed. The second member is joined to an area of part of a first surface of the first member, and includes a second electronic circuit including a semiconductor element formed of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the second member and an area of the first surface of the first member to which the second member is not joined. An inter-member connection wire on the interlayer insulating film couples the first and second electronic circuits through an opening in the interlayer insulating film. A shield structure including a first metal pattern disposed on the interlayer insulating film shields a shielded circuit, which is part of the first electronic circuit, in terms of radio frequencies.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi GOTO, Masayuki Aoike, Mikiko Fukasawa
  • Publication number: 20220200551
    Abstract: A power amplification device includes a first member in which a first circuit is formed, a second member in which a second circuit is formed, and a member-member connection conductor that electrically connects the first circuit and the second circuit to each other. The second member is mounted on the first member. The second circuit includes a first amplifier, which amplifies a radio frequency signal to output a first amplified signal. The first circuit includes a control circuit that controls an operation of the second circuit. At least part of a first termination circuit, which is connected to the first amplifier through the member-member connection conductor and which attenuates a harmonic wave component of the first amplified signal, is formed in the first member.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mitsunori SAMATA, Satoshi ARAYASHIKI, Koshi HIMEDA, Masayuki AOIKE
  • Publication number: 20220190124
    Abstract: A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 16, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shaojun MA, Shigeki KOYA, Masayuki AOIKE, Shinnosuke TAKAHASHI, Yasunari UMEMOTO, Masatoshi HASE
  • Publication number: 20220157808
    Abstract: A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.
    Type: Application
    Filed: October 18, 2021
    Publication date: May 19, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shinnosuke TAKAHASHI, Masayuki AOIKE, Takayuki TSUTSUI, Shigeki KOYA
  • Publication number: 20220122901
    Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shinnosuke TAKAHASHI, Masayuki AOIKE, Masatoshi HASE, Fumio HARIMA
  • Patent number: 11145607
    Abstract: A semiconductor chip includes a compound semiconductor substrate having a pair of main surfaces and a side surface therebetween, a circuit on one main surface of the pair of main surfaces, and first metals on the main surface. The first metals are positioned, in plan view of the main surface, closer to an outer edge of the main surface than the circuit, substantially in a ring shape to surround the circuit with gaps between first metals adjacent to each other. The semiconductor chip further includes second metals on the main surface. The second metals are positioned, in plan view of the main surface, between the circuit and the first metals or closer to the outer edge than the first metals. Also, the second metals each are positioned, in plan view of the side surface, such that at least a part thereof overlaps a gap between the first metals.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yusuke Tanaka, Fumio Harima, Masayuki Aoike, Koshi Himeda
  • Publication number: 20210288039
    Abstract: An RF circuit module includes a module substrate, a first substrate in which a first circuit is implemented, and a second substrate in which a second circuit is implemented. The first circuit includes a control circuit that controls an operation of the second circuit. The second circuit includes a radio-frequency amplifier circuit that amplifies an RF signal. The second substrate is mounted on the first substrate. The first substrate is disposed on the module substrate such that a circuit forming surface faces the module substrate. The first substrate and the second substrate have a circuit-to-circuit connection wire that electrically connects the first circuit and the second circuit without intervening the module substrate.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 16, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Masayuki AOIKE
  • Patent number: 10985123
    Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 20, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Masayuki Aoike, Takayuki Tsutsui
  • Publication number: 20200403088
    Abstract: A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 24, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Masayuki AOIKE
  • Publication number: 20200381324
    Abstract: A semiconductor device and a method for manufacturing a semiconductor device that enable characteristics to be improved are provided. A semiconductor device includes a substrate that has a first surface and a second surface that is located opposite the first surface, a first element that is disposed on the first surface, and a first resin layer that is disposed on the first surface and that is disposed around the first element in a plan view. The substrate includes a wiring layer. The first element includes a semiconductor layer, an electrode portion that is located on a surface of the semiconductor layer facing the substrate, and an insulating layer that is located opposite the electrode portion with the semiconductor layer interposed therebetween. The electrode portion is connected to the wiring layer. A height of the first resin layer from the first surface is more than a height of the first element from the first surface.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Teiji YAMAMOTO, Masayuki AOIKE, Hiroyuki NAGAI
  • Publication number: 20200321289
    Abstract: A semiconductor chip includes a compound semiconductor substrate having a pair of main surfaces and a side surface therebetween, a circuit on one main surface of the pair of main surfaces, and first metals on the main surface. The first metals are positioned, in plan view of the main surface, closer to an outer edge of the main surface than the circuit, substantially in a ring shape to surround the circuit with gaps between first metals adjacent to each other. The semiconductor chip further includes second metals on the main surface. The second metals are positioned, in plan view of the main surface, between the circuit and the first metals or closer to the outer edge than the first metals. Also, the second metals each are positioned, in plan view of the side surface, such that at least a part thereof overlaps a gap between the first metals.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 8, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yusuke TANAKA, Fumio HARIMA, Masayuki AOIKE, Koshi HIMEDA
  • Patent number: 10734310
    Abstract: A wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction. An insulating film is disposed on the wiring. A cavity entirely overlapping with the wiring as viewed from above is formed in the insulating film. A metal member electrically connected to the wiring via the cavity is disposed on the insulating film. The centroid of the cavity is displaced from that of the operating region of the corresponding unit transistor in the first direction. When the cavity having a centroid the closest to the operating region of a unit transistor is defined as the closest proximity cavity, the amount of deviation of the centroid of the closest proximity cavity from that of the operating region of the corresponding unit transistor in the first direction becomes greater from the center to the ends of the arrangement direction of the unit transistors.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kurokawa, Masayuki Aoike, Takayuki Tsutsui
  • Publication number: 20200161265
    Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Atsushi KUROKAWA, Masayuki AOIKE, Takayuki TSUTSUI
  • Patent number: 10580748
    Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 3, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kurokawa, Masayuki Aoike, Takayuki Tsutsui
  • Patent number: 10396148
    Abstract: A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 27, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinnosuke Takahashi, Masayuki Aoike
  • Publication number: 20190172807
    Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 6, 2019
    Inventors: Atsushi KUROKAWA, Masayuki AOIKE, Takayuki TSUTSUI
  • Publication number: 20190172773
    Abstract: A wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction. An insulating film is disposed on the wiring. A cavity entirely overlapping with the wiring as viewed from above is formed in the insulating film. A metal member electrically connected to the wiring via the cavity is disposed on the insulating film. The centroid of the cavity is displaced from that of the operating region of the corresponding unit transistor in the first direction. When the cavity having a centroid the closest to the operating region of a unit transistor is defined as the closest proximity cavity, the amount of deviation of the centroid of the closest proximity cavity from that of the operating region of the corresponding unit transistor in the first direction becomes greater from the center to the ends of the arrangement direction of the unit transistors.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 6, 2019
    Inventors: Atsushi KUROKAWA, Masayuki AOIKE, Takayuki TSUTSUI
  • Patent number: 10163749
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 25, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masayuki Aoike, Atsushi Kurokawa, Atsushi Kobayashi
  • Patent number: 10157812
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 18, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masayuki Aoike, Atsushi Kurokawa, Atsushi Kobayashi
  • Publication number: 20180308926
    Abstract: A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 25, 2018
    Inventors: Shinnosuke TAKAHASHI, Masayuki AOIKE