Patents by Inventor Masayuki Arimochi

Masayuki Arimochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11710855
    Abstract: An all-solid-state battery is provided that includes a cathode layer, an anode layer, and a solid electrolyte layer, in which a porosity of the solid electrolyte layer is equal to or less than 10%. Moreover, the batter includes a surface roughness Rz1 of the cathode layer and a surface roughness Rz2 of the anode layer, such that Rz1+Rz2?25.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 25, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Mamoru Nakashima, Masayuki Arimochi, Masamitsu Suzuki, Masahiro Morooka, Noriyuki Aoki, Keiko Hayashi
  • Patent number: 10903376
    Abstract: A light receiving/emitting element 11 includes: a light receiving/emitting layer 21 in which a plurality of compound semiconductor layers are stacked; and an electrode 30 having a first surface 30A and a second surface 30B and made of a transparent conductive material, in which the second surface faces the first surface 30A, and the electrode is in contact, at the first surface 30A, with the light receiving/emitting layer 21. The transparent conductive material contains an additive made of one or more metals, or a compound thereof, selected from the group consisting of molybdenum, tungsten, chromium, ruthenium, titanium, nickel, zinc, iron, and copper, and concentration of the additive contained in the transparent conductive material near an interface to the first surface 30A of the electrode 30 is higher than concentration of the additive contained in the transparent conductive material near the second surface 30B of the electrode 30.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 26, 2021
    Assignees: Sony Corporation, Suzhou Institute of Nano-Tech and Nano-Bionics
    Inventors: Tomomasa Watanabe, Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Ichiro Nomachi, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20200014071
    Abstract: An all-solid-state battery is provided that includes a cathode layer, an anode layer, and a solid electrolyte layer, in which a porosity of the solid electrolyte layer is equal to or less than 10%. Moreover, the batter includes a surface roughness Rz1 of the cathode layer and a surface roughness Rz2 of the anode layer, such that Rz1+Rz2?25.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Inventors: Mamoru NAKASHIMA, Masayuki ARIMOCHI, Masamitsu SUZUKI, Masahiro MOROOKA, Noriyuki AOKI, Keiko HAYASHI
  • Publication number: 20190260070
    Abstract: An all-solid-state battery that includes a positive electrode, a negative electrode, and an electrolyte layer. At least one of the positive electrode, the negative electrode, and the electrolyte layer includes a lithium ion conductor having an exothermic peak in a differential thermal analysis. The ionic conductivity on the side of the temperature higher than the rising temperature of the exothermic peak is lower than the ionic conductivity on the side of the temperature lower than the rising temperature of the exothermic peak.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Kenji Kishimoto, Masayuki Arimochi, Masahiro Morooka, Keisuke Shimizu, Masamitsu Suzuki
  • Publication number: 20180374970
    Abstract: A light receiving/emitting element 11 includes: a light receiving/emitting layer 21 in which a plurality of compound semiconductor layers are stacked; and an electrode 30 having a first surface 30A and a second surface 30B and made of a transparent conductive material, in which the second surface faces the first surface 30A, and the electrode is in contact, at the first surface 30A, with the light receiving/emitting layer 21. The transparent conductive material contains an additive made of one or more metals, or a compound thereof, selected from the group consisting of molybdenum, tungsten, chromium, ruthenium, titanium, nickel, zinc, iron, and copper, and concentration of the additive contained in the transparent conductive material near an interface to the first surface 30A of the electrode 30 is higher than concentration of the additive contained in the transparent conductive material near the second surface 30B of the electrode 30.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 27, 2018
    Inventors: Tomomasa WATANABE, Hiroshi YOSHIDA, Masao IKEDA, Shiro UCHIDA, Ichiro NOMACHI, Masayuki ARIMOCHI, Hui YANG, Shulong LU, Xinhe ZHENG
  • Patent number: 9905719
    Abstract: A multi-junction solar cell that is lattice-matched with a base, and that includes a sub-cell having a desirable band gap is provided. A plurality of sub-cells are laminated, each including first and second compound semiconductor layers. At least one predetermined sub-cell is configured of first layers and a second layer. In each of the first layers, a 1-A layer and a 1-B layer are laminated. In the second layer, a 2-A layer and a 2-B layer are laminated. A composition A of the 1-A layer and the 2-A layer is determined based on a value of a band gap of the predetermined sub-cell. A composition B of the 1-B layer and the 2-B layer is determined based on a difference between a base lattice constant of the base and a lattice constant of the composition A. Thicknesses of 1-B layer and 2-B layer are determined based on difference between base lattice constant and a lattice constant of composition B, and on thickness of the 1-A layer and thickness of 2-A layer.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: February 27, 2018
    Assignee: Sony Corporation
    Inventors: Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Takashi Tange, Masaru Kuramoto, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20150179840
    Abstract: A light receiving/emitting element 11 includes: a light receiving/emitting layer 21 in which a plurality of compound semiconductor layers are stacked; and an electrode 30 having a first surface 30A and a second surface 30B and made of a transparent conductive material, in which the second surface faces the first surface 30A, and the electrode is in contact, at the first surface 30A, with the light receiving/emitting layer 21. The transparent conductive material contains an additive made of one or more metals, or a compound thereof, selected from the group consisting of molybdenum, tungsten, chromium, ruthenium, titanium, nickel, zinc, iron, and copper, and concentration of the additive contained in the transparent conductive material near an interface to the first surface 30A of the electrode 30 is higher than concentration of the additive contained in the transparent conductive material near the second surface 30B of the electrode 30.
    Type: Application
    Filed: June 4, 2013
    Publication date: June 25, 2015
    Inventors: Tomomasa Watanabe, Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Masayuki Arimochi, Ichiro Nomachi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20140345681
    Abstract: There is provided a multi-junction solar cell that reduces contact resistance of a junction portion and is capable of performing energy conversion with high efficiency. The multi-junction solar cell includes a plurality of sub-cells 11, 12, 13, and 14 that are laminated, the plurality of sub-cells 11, 12, 13, and 14 being configured of a plurality of compound semiconductor layers 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, and 14C that are laminated. Amorphous connection layers 20A and 20B made of electrically-conductive material are provided in at least one place between the sub-cells 12 and 13 adjacent to each other.
    Type: Application
    Filed: September 3, 2012
    Publication date: November 27, 2014
    Inventors: Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Takashi Tange, Masaru Kuramoto, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20140345680
    Abstract: A multi-junction solar cell that is lattice-matched with a base, and that includes a sub-cell having a desirable band gap is provided. A plurality of sub-cells are laminated, each including first and second compound semiconductor layers. At least one predetermined sub-cell is configured of first layers and a second layer. In each of the first layers, a 1-A layer and a 1-B layer are laminated. In the second layer, a 2-A layer and a 2-B layer are laminated. A composition A of the 1-A layer and the 2-A layer is determined based on a value of a band gap of the predetermined sub-cell. A composition B of the 1-B layer and the 2-B layer is determined based on a difference between a base lattice constant of the base and a lattice constant of the composition A. Thicknesses of 1-B layer and 2-B layer are determined based on difference between base lattice constant and a lattice constant of composition B, and on thickness of the 1-A layer and thickness of 2-A layer.
    Type: Application
    Filed: September 3, 2012
    Publication date: November 27, 2014
    Inventors: Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Takashi Tange, Masaru Kuramoto, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20130250992
    Abstract: A semiconductor device comprising a substrate made of a material with a hexagonal crystal structure and having a substrate axis which is perpendicular to a principal surface of the substrate; and a nitride-based group III-V compound semiconductor layer grown directly on and in contact with the principal surface of the substrate without growing a buffer layer between the substrate and the nitride-based group III-V compound semiconductor layer, wherein, a direction of a growth axis of the semiconductor layer is substantially the same as a direction of the substrate axis of the substrate.
    Type: Application
    Filed: March 20, 2013
    Publication date: September 26, 2013
    Applicant: Sony Corppration
    Inventors: AKIRA OHMAE, KOTA TOKUDA, MASAYUKI ARIMOCHI, NOBUHIRO SUZUKI, MICHINORI SHIOMI, TOMONORI HINO, KATSUNORI YANASHIMA
  • Patent number: 8435880
    Abstract: In a method for manufacturing a semiconductor device, the method includes the step of growing a nitride-based III-V compound semiconductor layer, which forms a device structure, directly on a substrate without growing a buffer layer, the substrate being made of a material with a hexagonal crystal structure and having a principal surface that is oriented off at an angle of not less than ?0.5° and not more than 0° from an R-plane with respect to a direction of a C-axis.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: May 7, 2013
    Assignee: Sony Corporation
    Inventors: Akira Ohmae, Kota Tokuda, Masayuki Arimochi, Nobuhiro Suzuki, Michinori Shiomi, Tomonori Hino, Katsunori Yanashima
  • Patent number: 8242513
    Abstract: Disclosed herein is a method for growing a semiconductor layer which includes the step of growing a semiconductor layer of hexagonal crystal structure having the (11-22) or (10-13) plane direction on the (1-100) plane of a substrate of hexagonal crystal structure.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: August 14, 2012
    Assignee: Sony Corporation
    Inventors: Akira Ohmae, Masayuki Arimochi, Jugo Mitomo, Noriyuki Futagawa, Tomonori Hino
  • Publication number: 20110095401
    Abstract: In a method for manufacturing a semiconductor device, the method includes the step of growing a nitride-based III-V compound semiconductor layer, which forms a device structure, directly on a substrate without growing a buffer layer, the substrate being made of a material with a hexagonal crystal structure and having a principal surface that is oriented off at an angle of not less than ?0.5° and not more than 0° from an R-plane with respect to a direction of a C-axis.
    Type: Application
    Filed: October 18, 2010
    Publication date: April 28, 2011
    Applicant: SONY CORPORATION
    Inventors: Akira Ohmae, Kota Tokuda, Masayuki Arimochi, Nobuhiro Suzuki, Michinori Shiomi, Tomonori Hino, Katsunori Yanashima
  • Publication number: 20080283846
    Abstract: Disclosed herein is a method for growing a semiconductor layer which includes the step of growing a semiconductor layer of hexagonal crystal structure having the (11-22) or (10-13) plane direction on the (1-100) plane of a substrate of hexagonal crystal structure.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 20, 2008
    Applicant: SONY CORPORATION
    Inventors: Akira Ohmae, Masayuki Arimochi, Jugo Mitomo, Noriyuki Futagawa, Tomonori Hino