Abstract: Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2m-bit length) from a first register having a register length of at least 2m+1 bits, and also receives third and fourth complex data (each having 2m-bit length) from a second register having a register length of at least 2m+1 bits, to calculate a sum of real parts or imaginary parts of a complex product of the first and third complex data and a complex product of the second and fourth complex data. The complex-MAC unit adds the obtained sum of the real parts or imaginary parts to a stored value of the third register, and overwrites the third register with the cumulative total value. The third register has a register length of at least 2m+2 bits.

Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Abstract: Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2m-bit length) from a first register having a register length of at least 2m+1 bits, and also receives third and fourth complex data (each having 2m-bit length) from a second register having a register length of at least 2m+1 bits, to calculate a sum of real parts or imaginary parts of a complex product of the first and third complex data and a complex product of the second and fourth complex data. The complex-MAC unit adds the obtained sum of the real parts or imaginary parts to a stored value of the third register, and overwrites the third register with the cumulative total value. The third register has a register length of at least 2m+2 bits.

Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Abstract: A microprocessor has an instruction decode portion, a register file, a complex operation unit, and a data storage position determining mechanism. The complex operation unit performs complex operation, including complex multiplication, using first and second complex number data supplied from the register file based on an instruction decoded by the instruction decode portion, and outputs the result of the complex operation toward the register file. Furthermore, the data storage position determining mechanism determines the storage positions of the real part and imaginary part of output data of the complex operation unit in the register file such that the storage order of the real part and imaginary part of the output data in the register file is consistent with the storage orders of the real parts and imaginary parts of the first and second complex number data.

Abstract: A processor includes an instruction decoder, an instruction execution part and a register file. The instruction decoder is adapted to decode an instruction. The instruction execution part is adapted to execute processing corresponding to the instruction decoded by the instruction decoder. The register file is capable of storing load data from a data memory and supplying input data to the instruction execution part. The register file includes a plurality of registers, each of which is capable of holding a plurality of bits of data. Furthermore, the register file is configured to update the data held by the plurality of registers by shifting the data held by the plurality of registers among the plurality of registers.