Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

Abstract: Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

Abstract: Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

Abstract: A method and apparatus for detecting and correcting errors and erasures in product-coded data arrays by iterative syndrome processing array data in row major order and column major order. A first dense map is formed for classifying each row containing location indicia of random errors, their correction patterns, and pointers to rows containing erasure errors. This map is used to effectuate row array random error corrections in place in memory. A second dense map is formed of location indicia and correction patterns for each pair adjacent position within a column containing erasure errors as indexed by a counterpart row pointer. The second map is used to effectuate column array erasure corrections and random error corrections in place in memory.

Abstract: A method and apparatus for detecting and correcting errors and erasures in product-coded data arrays by iterative syndrome processing array data in row major order and column major order. A first dense map is formed for classifying each row containing location indicia of random errors, their correction patterns, and pointers to rows containing erasure errors. This map is used to effectuate row array random error corrections in place in memory. A second dense map is formed of location indicia and correction patterns for each pair adjacent position within a column containing erasure errors as indexed by a counterpart row pointer. The second map is used to effectuate column array erasure corrections and random error corrections in place in memory.

Abstract: An apparatus and method for decoding data encoded in a linear cyclic code with less hardware than the prior art decoding apparatus without sacrificing the processing speed are described. The polynomial arithmetic part 14 derives polynomials &sgr;(x), &ohgr;(x) by repeating calculation of the following Qi(x), exchange of polynomials between the register U_reg 180 and the register X_reg 184, and exchange of polynomials between the register Y_reg 182 and the register Z_reg 186 until the degree (deg Xreg) of the polynomial in the register X_reg 184 becomes smaller than [(d−h+1)/2] to solve the following recursive formula.

Abstract: A method and apparatus for efficiently encoding an ECC block for improving writing performance of a storage device using an ECC block format having a linear code such as a Reed-Solomon code is described. When the data f1 of a part of data sectors among a plurality of data sectors which form an ECC block F1 having a PO portion q1 formed with a linear code such as a Reed-Solomon code is updated with data f2 to obtain the ECC block F2 having the updated PO portion q2, the ECC block F1+F2 of the exclusive OR of the source data part of the ECC block F1 before updating and the ECC block F2 after updating is taken, so that the XOR of f1 and f2 (i.e. f1+f2) of the data f1 to be updated and the updated data f2 is obtained. The XOR of non-updated data sectors is 0. Then, when the ECC block F1+F2 of the XOR is encoded, the PO portion in the form of the XOR q1+q2 is obtained in accordance with the linearity of the Reed-Solomon code.

Abstract: It is one object of the present invention to perform efficient data transfer processing wherein, during decoding using a combination of product coding and erasure correction, real-time correction can be performed. To achieve the above object, provided is a method whereby a transfer mode is dynamically altered, in accordance with the state of a decoder, and in additional buffer, consisting of two banks, is added, so that the speed for the data transferring relative to the decoder is increased.