Patents by Inventor Masayuki Dohjo

Masayuki Dohjo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6078366
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: June 20, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori
  • Patent number: 6028652
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: February 22, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori
  • Patent number: 6008869
    Abstract: The present invention provides a display device substrate includes a first wiring layer formed on a substrate made of an insulating material, a second wiring layer formed to cross the first wiring layer, and an insulating film interposed between the first and second wiring layers at a cross point portion therebetween, wherein the first wiring layer is constituted by an electrode wiring layer made of a material containing aluminum as a main component and a surface covering layer formed by causing a refractory metal to denature the electrode wiring layer.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: December 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhisa Oana, Nobuki Ibaraki, Masayuki Dohjo, Yoshitaka Kamata
  • Patent number: 5966190
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: October 12, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori
  • Patent number: 5835177
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: November 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori
  • Patent number: 5646756
    Abstract: A liquid crystal display device having an array substrate. The substrate has: (1) an insulating transparent substrate that has a pixel region and a non-pixel region, (2) a plurality of thin film transistors disposed in a matrix pattern on a display screen, each thin film transistor having a gate insulating film that is produced by an atmosphere pressure chemical vapor deposition; (3) a plurality of display pixel electrodes formed on the pixel region of the insulating transparent substrate, each display pixel electrode being connected to each of the thin film transistors; and (4) a protecting film formed on the non-pixel region of the insulating transparent substrate, the protecting film extends from the non-pixel region and overlaps a peripheral portion of each of the display pixel electrodes that are disposed in a portion of the display screen by a width of 2 .mu.m to 7 .mu.m. The display also has a counter substrate that is disposed apart from and facing the array substrate.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: July 8, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Akira Kubo, Yasuharu Tanaka, Katsuhiko Inada
  • Patent number: 5170244
    Abstract: There is provided a semiconductor device using a molybdenum-tantalum alloy having a tantalum composition ratio of 30 to 84 atomic percent. Using this Mo-Ta alloy, there is provided an electrode interconnection material comprising a multi-layered structure having an underlying metal film having a crystalline form of a body-centered cubic system and overlying a molybdenum-tantalum alloy film having a tantalum composition ratio of above 84 atomic percent.
    Type: Grant
    Filed: April 8, 1991
    Date of Patent: December 8, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Yasuhisa Oana, Mitsushi Ikeda
  • Patent number: 5028551
    Abstract: There is provided a semiconductor device using a molybdenum-tantalum alloy having a tantalum composition ratio of 30 to 84 atomic percent. Using this Mo-Ta alloy, there is provided an electrode interconnection material comprising a multi-layered structure having an underlying metal film having a crystalline form of a body-centered cubic system and overlying a molybdenum-tantalum alloy film having a tantalum composition ratio of above 84 atomic percent.
    Type: Grant
    Filed: May 9, 1990
    Date of Patent: July 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Yasuhisa Oana, Mitsushi Ikeda
  • Patent number: 4975760
    Abstract: There is provided a semiconductor device using a molybdenum-tantalum alloy having a tantalum composition ratio of 30 to 84 atomic percent. Using this Mo-Ta alloy, there is provided an electrode interconnection material comprising a multi-layered structure having an underlying metal film having a crystalline form of a body-centered cubic system and overlying a molybdenum-tantalum alloy film having a tantalum composition ratio of above 84 atomic percent.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: December 4, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Yasuhisa Oana, Mitsushi Ikeda
  • Patent number: 4905066
    Abstract: A thin-film transistor comprising a substrate, a gate electrode formed on said substrate and made of molybdenum-tantalum alloy containing 60 to 85 atomic % of tantalum gate insulation film formed on said gate electrode and made of a laminated layer including silicon nitride film and oxide film formed by oxidizing the surface of said gate electrode, semiconductor film formed on said gate insulation film and contacting the silicon nitride film, and source and drain electrodes formed on the semiconductor film.
    Type: Grant
    Filed: April 19, 1989
    Date of Patent: February 27, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Yasuhisa Oana, Mitsushi Ikeda