Abstract: A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral registers and the first circuit; the first circuit including mirror registers, shift registers, in the write operation, serially outputting write data to the second circuit, and in the read operation, serially receiving read data supplied from the second circuit, and a first control block, in the read operation, generating a timing signal for writing the read data held in the shift registers into the corresponding mirror registers; the second circuit including shift registers and a second control block generating a second timing signal for either writing the write data held in the second shift register into the corresponding peripheral register or outputting data held in the peripheral register to the second shift register.

Abstract: The semiconductor IC has a nonvolatile memory including twin cells, a selector, and a sense circuit. When complementary data are written into a pair of nonvolatile memory cells of each twin cell, the pair of nonvolatile memory cells is set to be in a written state where one cell of the pair is set to one of low and high threshold voltages, and the other is set to the other threshold voltage. When non-complementary data are written into a pair of nonvolatile memory cells, for example, the memory cells both take the low threshold voltage and are made blank. The selector includes switching elements. During the blank-check action, switching elements of the selector are controlled to ON state. Then, the first total current of the twin cells forced to flow into the first input terminal of the sense circuit commonly is compared with the reference signal on the second input terminal, whereby whether the twin cells have been written or blank can be detected at a high speed.

Abstract: A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral registers and the first circuit; the first circuit including mirror registers, shift registers, in the write operation, serially outputting write data to the second circuit, and in the read operation, serially receiving read data supplied from the second circuit, and a first control block, in the read operation, generating a timing signal for writing the read data held in the shift registers into the corresponding mirror registers; the second circuit including shift registers and a second control block generating a second timing signal for either writing the write data held in the second shift register into the corresponding peripheral register or outputting data held in the peripheral register to the second shift register.

Abstract: A data transfer circuit making it possible to enhance the operational efficiency of a CPU, decrease the burden imposed to software, and reduce the scale of hardware.The data transfer circuit 10 is provided with a latch circuit 11 for latching signals EA, EB, EC indicating termination of the operation of a peripheral function portion, an operation result register 12 for storing operation results, an exclusive pointing register 13 designating a memory address for storing the contents of the operation result register 12 to a RAM, a selector 14 for selecting the exclusive pointing register 13 in response to the operation terminate signal EA, EB, EC, a selector 15 for selecting the operation result register 12 in response to the operation terminate signal EA, EB, EC, an OR gate 16 receiving the output of the latch circuit 11, a selector 17 for selecting a RAM address bus or the output signal from the selector 14, selectors 18, 19 for selecting the output signal, and a RAM 20.