Abstract: A computer system, such as a microprocessor-based computer system, which includes a program supervisory device for interrupting operations of the central processing unit of the computer system at any designated address, even in a case where the central processing unit has an instruction advance reading function. The interrupt address is stored in a register. A comparator outputs a coincidence signal when the interrupt address coincides with the current address supplied to the system memory. At that time, a multiplexer disposed in the system data bus disconnects the central processing unit from the memory and reconnects it via the system data bus to a register in which there has been prestored an interrupt or other instruction.