Patents by Inventor Masayuki Hoteida

Masayuki Hoteida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11879184
    Abstract: A manufacturing apparatus for a group-III nitride crystal, the manufacturing apparatus includes: a raw material chamber that produces therein a group-III element oxide gas; and a nurturing chamber in which a group-III element oxide gas supplied from the raw material chamber and a nitrogen element-containing gas react therein to produce a group-III nitride crystal on a seed substrate, wherein an angle that is formed by a direction along a shortest distance between a forward end of a group-III element oxide gas supply inlet to supply the group-III element oxide gas into the nurturing chamber and an outer circumference of the seed substrate placed in the nurturing chamber, and a surface of the seed substrate is denoted by “?”, wherein a diameter of the group-Ill element oxide gas supply inlet is denoted by “S”, wherein a distance between a surface, on which the seed substrate is placed, of a substrate susceptor that holds the seed substrate and a forward end of a first carrier gas supply inlet to supply a first
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: January 23, 2024
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Yusuke Mori, Masashi Yoshimura, Masayuki Imanishi, Shigeyoshi Usami, Junichi Takino, Masayuki Hoteida, Shunichi Matsuno
  • Publication number: 20220411962
    Abstract: A manufacturing apparatus for a group-III nitride crystal, the manufacturing apparatus includes: a raw material chamber that produces therein a group-III element oxide gas; and a nurturing chamber in which a group-III element oxide gas supplied from the raw material chamber and a nitrogen element-containing gas react therein to produce a group-III nitride crystal on a seed substrate, wherein an angle that is formed by a direction along a shortest distance between a forward end of a group-III element oxide gas supply inlet to supply the group-III element oxide gas into the nurturing chamber and an outer circumference of the seed substrate placed in the nurturing chamber, and a surface of the seed substrate is denoted by “?”, wherein a diameter of the group-Ill element oxide gas supply inlet is denoted by “S”, wherein a distance between a surface, on which the seed substrate is placed, of a substrate susceptor that holds the seed substrate and a forward end of a first carrier gas supply inlet to supply a first
    Type: Application
    Filed: June 24, 2022
    Publication date: December 29, 2022
    Applicant: Panasonic Holdings Corporation
    Inventors: Yusuke MORI, Masashi YOSHIMURA, Masayuki IMANISHI, Shigeyoshi USAMI, Junichi TAKINO, Masayuki HOTEIDA, Shunichi MATSUNO
  • Publication number: 20220403547
    Abstract: The manufacturing apparatus for a group-III compound semiconductor crystal according to the present disclosure comprises a reaction container. The reaction container has a raw material reaction section, a crystal growth section, and a gas flow channel. The raw material reaction section has a raw material reaction chamber, and a raw material gas nozzle. The crystal growth section has a substrate supporting member, and reactive gas nozzles. The gas flow channel includes a first flow channel, a second flow channel, and a connection portion. The first flow channel has a first opening, and the second flow channel has a second opening. The area of the second opening is configured to be larger than the area of the first opening. The connection portion connects the first opening and the second opening with each other. The gas flow channel forms a gas flow path in the reaction container. The substrate supporting member is disposed inside the gas flow path and located on the downstream side of the first opening.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Masayuki HOTEIDA, Junichi TAKINO, Shunichi MATSUNO
  • Publication number: 20220341056
    Abstract: A group Ill nitride crystal manufacturing apparatus includes a raw material chamber generating a group Ill elemental oxide gas, and a growth chamber allowing the group Ill element oxide gas supplied from the raw material chamber to react with a nitrogen element-containing gas to generate a group III nitride crystal on a seed substrate, and the growth chamber incudes a decomposition promoting part promoting decomposition of the unreacted nitrogen element- containing gas between the seed substrate and an exhaust port for discharging the unreacted group Ill oxide gas and the nitrogen element-containing gas.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 27, 2022
    Applicant: Panasonic Holdings Corporation
    Inventors: Yusuke MORI, Masashi YOSHIMURA, Masayuki IMANISHI, Shigeyoshi USAMI, Akira KITAMOTO, Junichi TAKINO, Masayuki HOTEIDA, Shunichi MATSUNO
  • Patent number: 11186922
    Abstract: An apparatus for producing a Group-III nitride semiconductor crystal includes a raw material reaction chamber, a raw material reactor which is provided in the raw material reaction chamber and configured to generate a Group-III element-containing gas, a board-holding member configured to hold a board in the raw material reaction chamber, a raw material nozzle configured to spray the Group-III element-containing gas toward the board, a nitrogen source nozzle configured to spray a nitrogen element-containing gas toward the board, in which, in a side view seen in a direction perpendicular to a vertical direction, a spray direction of the nitrogen source nozzle intersects with a spray direction of the raw material nozzle before the board, and a mixing part in which the Group-III element-containing gas and the nitrogen element-containing gas are mixed together is formed around the intersection as a center, a heater, and a rotation mechanism.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: November 30, 2021
    Assignee: PANASONIC CORPORATION
    Inventors: Masayuki Hoteida, Shunichi Matsuno, Junichi Takino
  • Publication number: 20200385886
    Abstract: An apparatus for producing a Group-III nitride semiconductor crystal includes a raw material reaction chamber, a raw material reactor which is provided in the raw material reaction chamber and generates a Group-III element-containing gas, a board-holding member configured to hold a board in the raw material reaction chamber, a raw material nozzle configured to spray the Group-III element-containing gas toward the board, a nitrogen source nozzle configured to spray a nitrogen element-containing gas toward the board, in which, in a side view seen in a direction perpendicular to a vertical direction, a spray direction of the nitrogen source nozzle intersects with a spray direction of the raw material nozzle before the board, and a mixing part in which the Group-III element-containing gas and the nitrogen element-containing gas are mixed together is formed around the intersection as a center, a heater for heating the raw material reaction chamber, the raw material nozzle, the nitrogen source nozzle, and the board
    Type: Application
    Filed: June 2, 2020
    Publication date: December 10, 2020
    Inventors: MASAYUKI HOTEIDA, SHUNICHI MATSUNO, JUNICHI TAKINO
  • Patent number: 9111839
    Abstract: An epitaxial wafer for a heterojunction type FET includes an AlN primary layer, a stepwisely composition-graded buffer layer structure, a superlattice buffer layer structure, a GaN channel layer, and a nitride semiconductor electron supply layer, which are sequentially provided on a Si substrate, the stepwisely composition-graded buffer layer structure including a plurality of AlGaN buffer layers provided on each other such that an Al composition ratio is sequentially reduced, an uppermost layer thereof having a composition of AlxGa1?xN (0<x), a plurality of sets of an AlyGa1?yN (y?1) superlattice constituting layer and an AlzGa1?zN (0<z<y) superlattice constituting layer being provided on each other alternately starting from one of the AlyGa1?yN superlattice constituting layer and the AlzGa1?zN superlattice constituting layer in the superlattice buffer layer structure, the AlxGa1?xN buffer layer and the AlzGa1?zN superlattice constituting layer satisfying x?0.05?z?x+0.05.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: August 18, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masayuki Hoteida, Nobuaki Teraguchi, Daisuke Honda, Nobuyuki Ito, Masakazu Matsubayashi, Haruhiko Matsukasa
  • Patent number: 8963165
    Abstract: A nitride semiconductor structure in which a first nitride semiconductor underlying layer is provided on a substrate having a recess portion and a projection portion provided between the recess portions at a surface thereof, the first nitride semiconductor underlying layer has at least 6 first oblique facet planes surrounding the projection portion on an outer side of the projection portion, and a second nitride semiconductor underlying layer buries the first oblique facet planes, a nitride semiconductor light emitting element, a nitride semiconductor transistor element, a method of manufacturing a nitride semiconductor structure, and a method of manufacturing a nitride semiconductor element are provided.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Araki, Shinya Yoshida, Haruhisa Takiguchi, Atsushi Ogawa, Takao Kinoshita, Tohru Murata, Takeshi Funaki, Masayuki Hoteida
  • Publication number: 20140353587
    Abstract: An epitaxial wafer for a heterojunction type FET includes an AlN primary layer, a stepwisely composition-graded buffer layer structure, a superlattice buffer layer structure, a GaN channel layer, and a nitride semiconductor electron supply layer, which are sequentially provided on a Si substrate, the stepwisely composition-graded buffer layer structure including a plurality of AlGaN buffer layers provided on each other such that an Al composition ratio is sequentially reduced, an uppermost layer thereof having a composition of AlxGa1—xN (0<x), a plurality of sets of an AlyGa1?yN (y?1) superlattice constituting layer and an AlzGa1?zN (0<z<y) superlattice constituting layer being provided on each other alternately starting from one of the AlyGa1?yN superlattice constituting layer and the AlzGa1?zN superlattice constituting layer in the superlattice buffer layer structure, the AlxGa1?xN buffer layer and the AlzGa1?zN superlattice constituting layer satisfying x?0.05?z?x+0.05.
    Type: Application
    Filed: January 15, 2013
    Publication date: December 4, 2014
    Inventors: Masayuki Hoteida, Nobuaki Teraguchi, Daisuke Honda, Nobuyuki Ito, Masakazu Matsubayashi, Haruhiko Matsukasa
  • Publication number: 20130277684
    Abstract: A nitride semiconductor structure in which a first nitride semiconductor underlying layer is provided on a substrate having a recess portion and a projection portion provided between the recess portions at a surface thereof, the first nitride semiconductor underlying layer has at least 6 first oblique facet planes surrounding the projection portion on an outer side of the projection portion, and a second nitride semiconductor underlying layer buries the first oblique facet planes, a nitride semiconductor light emitting element, a nitride semiconductor transistor element, a method of manufacturing a nitride semiconductor structure, and a method of manufacturing a nitride semiconductor element are provided.
    Type: Application
    Filed: December 21, 2011
    Publication date: October 24, 2013
    Inventors: Masahiro Araki, Shinya Yoshida, Haruhisa Takiguchi, Atsushi Ogawa, Takao Kinoshita, Tohru Murata, Takeshi Funaki, Masayuki Hoteida