Abstract: A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate, first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes, second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes, a first insulating film formed on the first diffusion layer, second insulating films formed on the side surfaces of the second gate electrodes, first silicide films formed on the first gate electrodes, second silicide films formed on the second gate electrodes, and third silicide films formed on the second diffusion layers.

Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

Abstract: A NAND type semiconductor device is disclosed, in which a first insulating film embedded between the memory cell gates and between the memory cell gates and the selecting gate does not contain nitrogen as a major component, a second insulating film is formed on the first insulating film, and an interlayer insulating film is formed on the second insulating film whose major component is different from a major component of the second insulating film.

Abstract: A semiconductor device includes a structure in which a first electrode layer, an inter-electrode insulating film and a second electrode layer are laminated in a main circuit in this order, and includes a capacitor element having a lower electrode formed of the same layer as the first electrode layer, a charge storage layer formed of the same layer as the inter-electrode insulating film, and an upper electrode formed of the second electrode layer. The semiconductor device further includes an opening portion formed in the charge storage layer, the opening portion having a bottom to which the lower electrode is exposed, and a first region electrically connected to the lower electrode via the opening portion and electrically isolated from the upper electrode, the first region being formed of the same layer as the second electrode layer.

Abstract: An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.