Abstract: A current fluctuating due to a load fluctuation is limited to protect a semiconductor switch. A protection circuit includes a switch circuit that turns on when a predetermined conduction voltage is applied thereto, and a sub-reactance circuit having a predetermined reactance value is connected in parallel to a main reactance circuit through which a high frequency current generated by a semiconductor switch flows. When the switch circuit is turned on, the main reactance circuit and the sub-reactance circuit are connected in parallel, and a high frequency current flows through this parallel connection circuit. The impedance value of the parallel connection circuit is set to be larger than the impedance value of the main reactance circuit so that the current is limited due to the turning on of the switch circuit, and thus, the semiconductor switch is protected.

Abstract: A current fluctuating due to a load fluctuation is limited to protect a semiconductor switch. A protection circuit includes a switch circuit that turns on when a predetermined conduction voltage is applied thereto, and a sub-reactance circuit having a predetermined reactance value is connected in parallel to a main reactance circuit through which a high frequency current generated by a semiconductor switch flows. When the switch circuit is turned on, the main reactance circuit and the sub-reactance circuit are connected in parallel, and a high frequency current flows through this parallel connection circuit. The impedance value of the parallel connection circuit is set to be larger than the impedance value of the main reactance circuit so that the current is limited due to the turning on of the switch circuit, and thus, the semiconductor switch is protected.

Abstract: According to one embodiment, semiconductor device includes a first semiconductor region; a second semiconductor region; a first insulating layer; a second insulating layer; a third semiconductor region; and an interconnect layer. The second semiconductor region is provided on the first semiconductor region, and second semiconductor region is connected to the first semiconductor region. The first insulating layer surrounds a first portion of the second semiconductor region. The second insulating layer surrounds a second portion of the second semiconductor region. The third semiconductor region is provided on the second portion of the second semiconductor region, the third semiconductor region is connected to the second portion, and the third semiconductor region is surrounded by the second insulating layer.