Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: In the evaluation of the randomness of an S-box, measures of resistance to higher order cryptanalysis, interpolation cryptanalysis, partitioning cryptanalysis and differential-linear cryptanalysis and necessary conditions for those measures to have resistance to each cryptanalysis are set, then for functions as candidates for the S-box, it is evaluated whether one or all of the conditions are satisfied, and those of the candidate functions for which one or all of the conditions are satisfied are selected as required. It is also possible to further evaluate the resistance of such selected functions to at least one of differential cryptanalysis and linear cryptanalysis and select those of the candidate functions which are resistant to at least one of the cryptanalyses as required.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit ((FL?1)) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit ((FL?1)) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: Permuted data (u1?, u2?, . . . , um?) of input data (u1, u2, . . . , un) expressed by the relationship [ u 1 ? u 2 ? ? u m ? ] = P ? [ u 1 u 2 ? u n ] , are obtained by expressing the permuted data uj? by uj?=ui?+Di, where j?i and calculate uj? for all of j.

Abstract: In an inverse calculation, x is road out of a storage means, [x/2] is calculated and stored therein as b, a lent significant bit of b is stored as a, [(ax+b)/2] is calculated and stored as updated b, and low-order two bits of x are stored as y. Then, for i=1, 2, . . . , n?1, by is calculated, a is updated with ?by, [(b+ax)/(2^(2i))] is calculated and stored as updated b, and y+a2^(2i) is calculated and stored as updated y, where y is road out as the result of inverse calculation.

Abstract: A plurality of round processing parts (38) are provided each of which contains a nonlinear function part (304), and each nonlinear function part (304) comprises: a first key-dependent linear transformation part (341) which performs a linear transformation based on a subkey; a splitting part (342) which splits the output from the first key-dependent linear transformation part into n pieces of subdata; a first nonlinear transformation part (343) which nonlinearly transforms those pieces of subdata, respectively; a second key-dependent linear transformation part (344) which linearly transforms those nonlinearly transformed outputs based on a subkey and outputs n pieces of transformed subdata; a second nonlinear transformation part (345) which nonlinearly transforms those transformed subdata; and a combining part (346) which combines the nonlinearly transformed outputs.

Abstract: In a method for permuting and dividing 16 pieces of k-bit data held in 4k-bit long registers T0, T1, T2 and T3, k being an integer, the data of each register Ti is ANDed with a desired one of mask data (00ffff00), (ff0000ff), (0000ffff) and (ffff0000), and such ANDs are ORed to obtain desired permuted data.

Abstract: In a method for permuting and dividing 16 pieces of k-bit data held in 4 k-bit long registers T0. T1, T2 and T3, k being an integer, the data of each register Ti is ANDed with a desired one of mask data (00ffff00), (ff0000ff), (0000ffff) and (ffff0000), and such ANDs are ORed to obtain desired permuted data.

Abstract: In a method for permuting and dividing 16 pieces of k-bit data held in 4k-bit long registers T0. T1, T2 and T3, k being an integer, the data of each register Ti is ANDed with a desired one of mask data (00ffff00), (ff0000ff), (0000ffff) and (ffff0000), and such ANDs are ORed to obtain desired permuted data.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL−1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL−1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: A personal computer has a print image developing means and a data compression means including a fixed rate compression. A color printer has a data extension means, a color correction means, a gamma correction means, a first halftoning means, an image area segmentation means, and a second halftoning means. The transmission time of a print image can be shortened necessarily to less than a constant time, and further, since an enormous memory for extension is unnecessary, a low cost printer can be provided.

Abstract: In a halftoning unit of a laser printer and the like, a high speed, high density and high gradations halftoning is realized by multi-value implementation by clustered dot concentrated dither halftoning (known as a sub-matrix method) and PWM distributing gradation among the plurality of halftone dots with a small memory and circuit. For this purpose, the value of the difference between an input gradation value ni and a threshold value nc, &Dgr;n=ni−nc, is shortened within a range of 0 to &Dgr;h and the lower s bit of &Dgr;h is removed by a round-down or round-up process. Meanwhile, a threshold array is generated from an extended threshold pattern obtained by combining threshold patterns of 2s whose threshold interval is &Dgr;h, i.e. &Dgr;Ah×K, &Dgr;h×K+1, . . . , &Dgr;×K+2(s−1). Thereby, a halftone dot dither process in which the PWM gradation increases distributively among the 2s dots may be realized with a small scale memory and circuit.

Abstract: A message delivery system which can guarantee the authenticity of a user, the reliability of a message delivery, and the authenticity of the message delivery, while preventing an illegal act, and which can prove them at a later time. The system has an information provider terminal including a user authentication unit for carrying out a user authentication of the user according to a zero knowledge interactive proof protocol using check bits E generated according to a work key W, and a transmission unit for transmitting to the user a ciphertext C in which a message M to be delivered to the user is enciphered according to a secret key cryptosystem by using the work key W, and the check bits E. The system also has a user terminal including a message reception unit for taking out the work key W by using at least the check bits E, and obtaining the message M by deciphering the ciphertext C according to the secret key cryptosystem by using the work key W.