Patents by Inventor Masayuki Kasamoto

Masayuki Kasamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5943280
    Abstract: When a special operation mode is instructed, a test oscillation circuit operating at a cycle shorter than a refresh oscillation circuit specifying the cycle of self refresh is activated according to an external row address strobe signal. The internal row address strobe signal is provided to row related control circuitry via a selector. An internal row address strobe signal can be rendered active at a cycle shorter than the cycle of the external row address strobe signal, to carry out row selection. A row is selected at a cycle shorter than the transition cycle of an external signal.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 24, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukihiro Tsukamoto, Koji Kimura, Masaki Nishimoto, Masayuki Kasamoto, Naotaka Okada, Kazuhisa Uetsuki, Masakatsu Murakami, Shigekazu Aoki, Zengcheng Tian, Shin Sekiya, Akihiro Shirai
  • Patent number: 5379174
    Abstract: In a semiconductor integrated circuit device including a substrate bias voltage generating circuit supplying a substrate bias voltage to internal circuit performing original functions and a substrate where the internal circuit is formed, an N channel MOS transistor is provided between the internal circuit and power supply pad receiving an external voltage Vcc for driving the circuit. The transistor is controlled such that it is rendered conductive when substrate potential V.sub.SB is higher than the threshold voltage of MOS transistor and non-conductive when potential V.sub.SB is lower than the threshold voltage. Since supply of power supply voltage Vcc to the internal circuit is interrupted if latch-up is caused in the internal circuit and substrate potential V.sub.SB rises, internal circuit is immediately freed from the latch-up state even if latch-up is caused. Therefore, the internal circuit is protected from being heated or destructed by a current due to the latch-up.
    Type: Grant
    Filed: July 13, 1992
    Date of Patent: January 3, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masayuki Kasamoto