Patents by Inventor Masayuki Kokado

Masayuki Kokado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5240867
    Abstract: A semiconductor integrated circuit comprises a substrate of a first semiconductor type doped by a first impurity element with a first impurity density, the first semiconductor type being one of p-type and n-type semiconductors, a conductive layer formed on a back surface of the substrate, a first layer of a second semiconductor type doped by a second impurity element different from the first impurity element and formed on a front surface of the substrate, the second semiconductor type being the other of the p-type and n-type semiconductors and the first layer having a second impurity density lower than the first impurity density, a second layer of the first semiconductor type formed on the first layer for forming circuit elements therein, a first region of the second semiconductor type extending from a top surface of the first layer and reaching a top surface of the second layer, and a second region of the first semiconductor type extending from a top surface of the substrate and reaching the top surface of s
    Type: Grant
    Filed: September 11, 1991
    Date of Patent: August 31, 1993
    Assignee: Fujitsu Limited
    Inventors: Kouichi Suzuki, Norihito Miyoshi, Makoto Yoshida, Masayuki Kokado
  • Patent number: 5231345
    Abstract: A semiconductor integrated circuit device includes an array of a plurality of basic circuits, and a test circuit which tests a logic circuit formed of at least one of the basic circuits. The test circuit includes a plurality of select lines, a plurality of read lines, and a plurality of switching circuits. Each of the switching circuits has a first bipolar transistor having a base coupled to at least one test point of the corresponding basic circuit, a collector and an emitter both connectable to connect the test point to a corresponding one of the read lines when a corresponding one of the switching circuits is turned ON in response to a select signal supplied via a corresponding one of the select lines. The test circuit also includes a select line selecting circuit for selecting one of the select lines and for outputting the select signal to a selected one of the select lines. The select signal turns ON selected first bipolar transistors among the plurality of first bipolar transistors.
    Type: Grant
    Filed: March 8, 1991
    Date of Patent: July 27, 1993
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Katakura, Makoto Yoshida, Masayuki Kokado
  • Patent number: 5072274
    Abstract: A semiconductor integrated circuit is supplied with a power source voltage to a circuit element forming layer thereof from a conductive layer through a substrate and a certain region made of a semiconductor type identical to that of the substrate. The conductive layer is formed on a back surface of the substrate, and the certain region makes contact with a front surface of the substrate. The circuit element forming layer is provided on the front surface side of the substrate and connects to the certain region. Alternatively, a region may be provided to extend from the circuit element forming layer to the substrate so as to provide a conductive path for supplying the power source voltage from the back surface of the substrate.
    Type: Grant
    Filed: December 10, 1990
    Date of Patent: December 10, 1991
    Assignee: Fujitsu Limited
    Inventor: Masayuki Kokado
  • Patent number: 5065216
    Abstract: A semiconductor integrated circuit comprises a substrate of a first semiconductor type doped by a first impurity element with a first impurity density, the first semiconductor type being one of p-type and n-type semiconductors, a conductive layer formed on a back surface of the substrate, a first layer of a second semiconductor type doped by a second impurity element different from the first impurity element and formed on a front surface of the substrate, the second semiconductor type being the other of the p-type and n-type semiconductors and the first layer having a second impurity density lower than the first impurity density, a second layer of the first semiconductor type formed on the first layer for forming circuit elements therein, a first region of the second semiconductor type extending from a top surface of the first layer and reaching a top surface of the second layer, and a second region of the first semiconductor type extending from a top surface of the substrate and reaching the top surface of s
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: November 12, 1991
    Assignee: Fujitsu Ltd.
    Inventors: Kouichi Suzuki, Norihito Miyoshi, Makoto Yoshida, Masayuki Kokado
  • Patent number: 4928025
    Abstract: An emitter coupled logic circuit includes variable impedance circuit which is connected to at least one of two output terminals of the ECL circuit for variably providing an impedance connected to the one output terminal. An impedance to be provided when both the levels of the two outputs are at a high-level is set to be smaller than an impedance to be provided when at least one of the two outputs is at a low-level.
    Type: Grant
    Filed: July 1, 1988
    Date of Patent: May 22, 1990
    Assignee: Fujitsu Limited
    Inventor: Masayuki Kokado
  • Patent number: 4877977
    Abstract: A semiconductor integrated circuit having an emitter follower circuit coupled with an output of a logic circuit includes the following. A first emitter follower circuit receives an output signal of a logic circuit such as an emitter coupled logic circuit. An output signal obtained at an emitter output of the first emitter follower circuit forms a finalized output signal of the logic circuit. A second emitter follower circuit receives a signal in phase with the output signal of the logic circuit. A detecting circuit detects a difference in level between the output signal of the first emitter follower circuit and an output signal of the second emitter follower circuit. A driving circuit drives a load capacitance coupled with the emitter output of the first emitter follower circuit during a period when the detecting circuit detects the difference.
    Type: Grant
    Filed: May 27, 1988
    Date of Patent: October 31, 1989
    Assignee: Fujitsu Limited
    Inventor: Masayuki Kokado
  • Patent number: 4729882
    Abstract: A process for cleaning gaseous emissions containing mercury (Hg) comprises the steps of adding a chlorine-containing material to the mercury-containing gaseous emissions and heating the mixture to convert the mercury into water-soluble mercuric chloride (HgCl.sub.2); scrubbing the water-soluble mercuric chloride with wash water and fixing the same as chlorocomplex ion (HgCl.sub.4.sup.-2) stable in liquid; and thereafter subjecting the washings from the scrubbing step to coagulating sedimentation and thereby fixing and insolubilizing the mercury in the resulting sludge.
    Type: Grant
    Filed: September 3, 1985
    Date of Patent: March 8, 1988
    Assignee: Tokyo Metropolitan Environmental Service Corporation
    Inventors: Akira Ide, Tsutomu Shigenaka, Masayuki Kokado, Shigeru Kondo
  • Patent number: 4631567
    Abstract: A semiconductor device comprises an internal circuit and an electrostatic destruction preventing circuit connected between a predetermined electrical potential point and a signal input terminal with respect to the internal circuit. The electrostatic destruction preventing circuit comprises a PNP-transistor having its emitter connected to the predetermined electrical potential point, an NPN-transistor having its emitter connected to said signal input terminal and said internal circuit, collector connected to the base of the PNP-transistor, and base connected to the collector of said PNP-transistor, and a resistor connected between the base of the PNP-transistor and the base of the NPN-transistor.
    Type: Grant
    Filed: January 23, 1985
    Date of Patent: December 23, 1986
    Assignee: Fujitsu Limited
    Inventors: Masayuki Kokado, Hidezi Sumi
  • Patent number: 4546272
    Abstract: An ECL circuit includes a differential pair of transistors, a set transistor, and a set resistor connected between the emitters of the differential pair of transistors and the emitter of the set transistor. The output of the ECL circuit can be fixed securely to a "high" level only by applying a "high" level signal having the same level as the "high" level signal of the data input to the base of the set transistor.
    Type: Grant
    Filed: May 27, 1983
    Date of Patent: October 8, 1985
    Assignee: Fujitsu Limited
    Inventors: Hirokazu Suzuki, Masayuki Kokado
  • Patent number: 4437021
    Abstract: A line driver circuit for driving a unit located a long distance away through a long transmission line, comprising an output stage having an emitter follower including transistors in which an output-stage transistor provides an output signal of a high potential or a low potential in response to the electric potential of an input signal. A discharge pass is connected to the base of the output-stage transistor, for drawing charges on the base of the output-stage transistor off thereof and thus shortening the fall time of the output waveform.
    Type: Grant
    Filed: October 7, 1981
    Date of Patent: March 13, 1984
    Assignee: Fujitsu Limited
    Inventors: Hideji Sumi, Masayuki Kokado
  • Patent number: 4413300
    Abstract: A line driver circuit having a protective circuit against excess currents, which includes a protective transistor for limiting the output current of an output-stage emitter-follower transistor. A detecting means for detecting the output current of the emitter-follower transistor and a pull-up transistor for pulling up the base potential of the protective transistor are provided. Before the output current becomes too large, the detecting means detects the output current to turn on the pull-up transistor. Then the base potential of the protective transistor is pulled up to turn on the protective transistor. As a result the base current of the emitter-follower transistor is decreased, so that the emitter-follower transistor is protected from being thermally destroyed.
    Type: Grant
    Filed: October 13, 1981
    Date of Patent: November 1, 1983
    Assignee: Fujitsu Limited
    Inventors: Hideji Sumi, Masayuki Kokado