Patents by Inventor Masayuki Moriya

Masayuki Moriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12172240
    Abstract: The present invention relates to solder particles, each of which partially has a flat portion in the surface. By using these solder particles, electrodes facing each other are able to be appropriately connected, thereby achieving an anisotropic conductive material that exhibits excellent conduction reliability and excellent insulation reliability.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 24, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Kunihiko Akai, Yoshinori Ejiri, Yuuhei Okada, Toshimitsu Moriya, Shinichirou Sukata, Masayuki Miyaji
  • Patent number: 12100923
    Abstract: A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: September 24, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Kunihiko Akai, Masayuki Miyaji, Junichi Kakehata, Yoshinori Ejiri, Toshimitsu Moriya
  • Patent number: 9396959
    Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 19, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Takayuki Enda, Masayuki Moriya
  • Publication number: 20120248597
    Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.
    Type: Application
    Filed: June 14, 2012
    Publication date: October 4, 2012
    Inventors: Takayuki ENDA, Masayuki MORIYA
  • Patent number: 8222147
    Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: July 17, 2012
    Assignee: Spansion LLC
    Inventors: Takayuki Enda, Masayuki Moriya
  • Publication number: 20070015366
    Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 18, 2007
    Inventors: Takayuki Enda, Masayuki Moriya
  • Patent number: D265296
    Type: Grant
    Filed: May 6, 1980
    Date of Patent: July 6, 1982
    Assignee: Kabushiki Kaisha Sendai Seimitsu Zairyo Kenkyujho
    Inventors: Hiroshi Wanibuchi, Masayuki Moriya, Yoshiro Yanagi