Abstract: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.

Abstract: In a calculator 520, a test bench 521 for event-driven asynchronous simulation described in an HDL is stored. An input-related description portion in the test bench 521 is input to an LSI tester 510 and converted into a signal input to a DUT 500, and then the signal input is applied to the DUT 500. Thereafter, an output signal produced from the DUT in response to the signal input is input to the LSI tester 510 and compared with an output signal obtained from a voltage condition table and the like, thereby determining the level of the output signal. This comparison result is input to the calculator 520, in which the comparison result is compared with an expected value and output waveform data described in the HDL test bench 521, so as to make a pass/failure determination for the DUT 500. It is thus possible to test the LSI (DUT) under the same conditions as the LSI is actually used in a product.

Abstract: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.

Abstract: The invention relates to a method for reducing the time required to test the functions of a semiconductor device. Test modules, each having a plurality of test statements, are created for testing predetermined functions of the device. Common test statements are extracted from the test modules. A test program is then produced by sequentially arranging the extracted statement(s) and the remaining statements from the test modules.

Abstract: The present invention offer a semiconductor testing apparatus which is able to test all functions of a semiconductor device in a short time. The semiconductor testing apparatus comprises a conditional imperative statement part storing therein all statements concerning conditional setting for the measuring means, a first comparison part for comparing statement received from the control means with the respective statements stored in the conditional imperative statement part, and a second comparison part for comparing the statements received from the control means with the respective statements stored in the memory means.