Patents by Inventor Masayuki Nagamatsu

Masayuki Nagamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10297516
    Abstract: A semiconductor device includes a semiconductor element, a base, and an outer packaging resin. The base has a mounting surface, on which the semiconductor element is mounted, and a groove provided around the semiconductor element on the mounting surface. An outer packaging resin covers the semiconductor element and the base, and is fixed to the base by filling the groove. A bottom of the groove includes a first recess-projection having a first amplitude and a first repetition interval along an extending direction of the groove. The first recess-projection includes a second recess-projection having a second amplitude smaller than the first amplitude and a second repetition interval shorter than the first repetition interval along the extending direction of the groove.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 21, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masayuki Nagamatsu, Shinya Marumo, Junichi Kimura, Tatsuya Kunisato, Ryosuke Usui
  • Publication number: 20180197802
    Abstract: A semiconductor device includes a semiconductor element, a base, and an outer packaging resin. The base has a mounting surface, on which the semiconductor element is mounted, and a groove provided around the semiconductor element on the mounting surface. An outer packaging resin covers the semiconductor element and the base, and is fixed to the base by filling the groove. A bottom of the groove includes a first recess-projection having a first amplitude and a first repetition interval along an extending direction of the groove. The first recess-projection includes a second recess-projection having a second amplitude smaller than the first amplitude and a second repetition interval shorter than the first repetition interval along the extending direction of the groove.
    Type: Application
    Filed: March 1, 2017
    Publication date: July 12, 2018
    Inventors: MASAYUKI NAGAMATSU, SHINYA MARUMO, JUNICHI KIMURA, TATSUYA KUNISATO, RYOSUKE USUI
  • Patent number: 9307630
    Abstract: A device mounting board comprises: a heat dissipating substrate formed of a material containing at least one metal material selected from a group including Al, Mg, and Ti; an insulting resin layer laminated on the heat dissipating substrate; and a wiring layer laminated on the insulating resin layer, and on which a power module is to be mounted. The heat dissipating substrate comprises a random porous layer arranged such that it faces the insulating resin layer, and having cavities elongated in respective random directions.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 5, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Nagamatsu, Mayumi Nakasato, Yasuyuki Yanase
  • Patent number: 9271389
    Abstract: A device mounting board includes a metallic substrate, an oxide film formed such that the surfaces of the metallic form are oxidized, an insulating resin layer disposed on the oxide film facing one main surface of the metallic layer, and a wiring layer disposed on the insulating resin layer. The film thickness of a certain partial region of the oxide film disposed below a first semiconductor device is greater than that of the other regions surrounding the partial region of the oxide film. Conversely, the film thickness of the insulating resin layer underneath a second semiconductor device is less than that of the insulating resin layer underneath the first semiconductor device.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 23, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasuhiro Kohara, Masayuki Nagamatsu, Koutaro Deguchi
  • Patent number: 9035454
    Abstract: Prepared in advance is a substrate formed of metallic material where slits are formed between mounting regions. Oxide films are generated all over the substrate including end faces of the substrate. Exposed are only lateral faces corresponding to the cross sections cut when tie bars are cut. This structure and the fabrication method minimize the area of cutting faces in the metallic material.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: May 19, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Nagamatsu, Mayumi Nakasato, Masurao Yoshii, Yasuhiro Kohara, Kotaro Deguchi
  • Patent number: 9024446
    Abstract: Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 5, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryosuke Usui, Yusuke Igarashi, Yasunori Inoue, Mayumi Nakasato, Masayuki Nagamatsu, Yasuhiro Kohara
  • Publication number: 20140084452
    Abstract: Prepared in advance is a substrate formed of metallic material where slits are formed between mounting regions. Oxide films are generated all over the substrate including end faces of the substrate. Exposed are only lateral faces corresponding to the cross sections cut when tie bars are cut. This structure and the fabrication method minimize the area of cutting faces in the metallic material.
    Type: Application
    Filed: November 27, 2013
    Publication date: March 27, 2014
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masayuki NAGAMATSU, Mayumi NAKASATO, Masurao YOSHII, Yasuhiro KOHARA, Kotaro DEGUCHI
  • Publication number: 20140078687
    Abstract: A device mounting board includes a metallic substrate, an oxide film formed such that the surfaces of the metallic form are oxidized, an insulating resin layer disposed on the oxide film facing one main surface of the metallic layer, and a wiring layer disposed on the insulating resin layer. The film thickness of a certain partial region of the oxide film disposed below a first semiconductor device is greater than that of the other regions surrounding the partial region of the oxide film. Conversely, the film thickness of the insulating resin layer underneath a second semiconductor device is less than that of the insulating resin layer underneath the first semiconductor device.
    Type: Application
    Filed: November 25, 2013
    Publication date: March 20, 2014
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Yasuhiro KOHARA, Masayuki NAGAMATSU, Koutaro DEGUCHI
  • Patent number: 8440915
    Abstract: A semiconductor device is of a PoP structure such that first electrode portions provided on a first device mounting board constituting a first semiconductor module and second electrode portions provided in a second semiconductor module are joined together by solder balls. A first insulating layer having an opening is provided on one main surface of an insulating resin layer which is a substrate, and an electrode portion, whose top portion protrudes above the top surface of the first insulating layer, is formed in the opening. A second insulating layer is provided on top of the first insulating layer in the periphery of the top portion of the first electrode portion; the second insulting layer is located slightly apart from the top portion of the first electrode portion. The first electrode portion is shaped such that the top portion is formed by a curved surface or formed by a curved surface and a plane surface smoothly connected to the curved surface.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: May 14, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masayuki Nagamatsu, Kiyoshi Shibata, Takanori Hayashi
  • Patent number: 8269298
    Abstract: A semiconductor module includes a lower wiring substrate having a semiconductor device mounted and an upper wiring substrate having an opening in a position corresponding to the semiconductor device and having a packaging-component mountable region around the opening. The lower wiring substrate and the upper wiring substrate are electrically connected to each other via a plurality of solder balls provided around the semiconductor device. The solder balls are covered with light blocking under-fills.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 18, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Yasunori Inoue
  • Patent number: 8258409
    Abstract: Provided are a circuit board with enhanced moisture resist and the method of manufacturing the circuit board, and a circuit device and a method of manufacturing the circuit device. A circuit board of the present invention includes: a substrate; wirings formed on the main surface of the substrate; a cover layer covering the wirings excluding the regions to be connectors; back electrodes formed on the bottom surface of the substrate; and through-hole electrodes formed so as to penetrate the substrate, and thereby connecting the wirings and the back electrodes. On surfaces of each of the wirings in this circuit board, convex portions on the periphery of the substrate are set larger in width than convex portions in a center portion of the substrate. With this configuration, adhesion reliability between the wirings and the cover layer under a thermal cycle load can be enhanced.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: September 4, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Kohara, Kiyoshi Shibata, Masayuki Nagamatsu, Ryosuke Usui, Toshiya Shimizu
  • Publication number: 20120098137
    Abstract: Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.
    Type: Application
    Filed: June 30, 2010
    Publication date: April 26, 2012
    Inventors: Ryosuke Usui, Yusuke Igarashi, Yasunori Inoue, Mayumi Nakasato, Masayuki Nagamatsu, Yasuhiro Kohara
  • Patent number: 8153186
    Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: April 10, 2012
    Assignee: Sanyo Eletric Co., Ltd.
    Inventors: Masayuki Nagamatsu, Ryosuke Usui
  • Patent number: 8068343
    Abstract: A semiconductor module is provided, which is capable of suppressing the deterioration of reliability and improving heat radiation. The semiconductor module includes: a semiconductor substrate in which electrodes of a circuit element are formed on its surface; a re-wiring pattern connected to the electrodes to ensure large pitch of the electrodes; an electrode integrally formed with the re-wiring pattern; an insulating layer formed on a rear surface of the semiconductor substrate; a radiator formed on the insulating layer; and projections integrally formed with the radiator and penetrating the insulating layer to connect to the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: November 29, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20110174527
    Abstract: A semiconductor device is of a PoP structure such that first electrode portions provided in a first semiconductor module and second electrode portions provided in a second semiconductor module are joined together by solder balls. The first electrode has a first conductor having the same thickness as that of a wiring layer provided in an insulating layer, a second conductor formed on the first conductor, a gold plating layer provided on the second conductor.
    Type: Application
    Filed: June 30, 2009
    Publication date: July 21, 2011
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Kiyoshi Shibata
  • Publication number: 20110100696
    Abstract: A semiconductor device is of a PoP structure such that first electrode portions provided on a first device mounting board constituting a first semiconductor module and second electrode portions provided in a second semiconductor module are joined together by solder balls. A first insulating layer having an opening is provided on one main surface of an insulating resin layer which is a substrate, and an electrode portion, whose top portion protrudes above the top surface of the first insulating layer, is formed in the opening. A second insulating layer is provided on top of the first insulating layer in the periphery of the top portion of the first electrode portion; the second insulting layer is located slightly apart from the top portion of the first electrode portion. The first electrode portion is shaped such that the top portion is formed by a curved surface or formed by a curved surface and a plane surface smoothly connected to the curved surface.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 5, 2011
    Inventors: Masayuki NAGAMATSU, Kiyoshi Shibata, Takanori Hayashi
  • Publication number: 20100288550
    Abstract: There has been such a problem that conventional element mounting substrates and circuit devices using such substrates are not easily thinned, as there is a wiring layer formed on each of the substrates and that a part of the wiring layer is protruded and used as a bump electrode. In an element mounting substrate of this invention and a circuit device using such substrate, a through hole is arranged on an insulating base material, and a wiring layer is protruded from the surface of the insulating base material through the through hole. The protruding section of the wiring layer is used as a bump electrode, and a semiconductor element is mounted on the insulating base material. With such structure, the element mounting substrate is thinned, and the circuit device using such substrate is also thinned.
    Type: Application
    Filed: July 28, 2008
    Publication date: November 18, 2010
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20100244171
    Abstract: A semiconductor module includes a lower wiring substrate having a semiconductor device mounted and an upper wiring substrate having an opening in a position corresponding to the semiconductor device and having a packaging-component mountable region around the opening. The lower wiring substrate and the upper wiring substrate are electrically connected to each other via a plurality of solder balls provided around the semiconductor device. The solder balls are covered with light blocking under-fills.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 30, 2010
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20100193937
    Abstract: A wiring layer including external connection regions is provided on a main surface of an insulating resin layer on a side opposite to that of a semiconductor device mounting face. The wiring layer is coated with a protection layer. An opening is provided to the protection layer such that each external connection region is exposed. Each external connection region has a curved surface recessed toward the insulating resin layer side. The entire area of each opening is filled with a solder ball for mounting a substrate, and the recess of each external connection region is filled with the solder ball, thereby connecting each solder ball to the intermediate layer.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 5, 2010
    Inventors: Masayuki Nagamatsu, Yasuhiro Kohara, Ryosuke Usui
  • Publication number: 20090304910
    Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.
    Type: Application
    Filed: August 14, 2009
    Publication date: December 10, 2009
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Masayuki Nagamatsu, Ryosuke Usui