Abstract: A display control apparatus includes at least one output control unit, and each output control unit comprises: a tri-state buffer receiving, as a signal input, a one-bit color signal, and receiving, as a control input, a one-bit intermediate color control signal for controlling an intermediate color of the color signal, and setting its output in one of the following three states: a state of outputting a first voltage, a state of outputting a second voltage, and a high impedance state, on the basis of the color signal and the intermediate color control signal; a first resistor having an end connected to a power supply, and the other end connected to the output of the tri-state buffer; and a second resistor having an end connected to the ground, and the other end connected to the output of the tri-state buffer. Therefore, it is possible to provide a display control apparatus that is able to perform intermediate color display, with reduced manufacturing cost and reduced power consumption.

Abstract: A display control apparatus includes at least one output control unit, and each output control unit comprises: a tri-state buffer receiving, as a signal input, a one-bit color signal, and receiving, as a control input, a one-bit intermediate color control signal for controlling an intermediate color of the color signal, and setting its output in one of the following three states: a state of outputting a first voltage, a state of outputting a second voltage, and a high impedance state, on the basis of the color signal and the intermediate color control signal; a first resistor having an end connected to a power supply, and the other end connected to the output of the tri-state buffer; and a second resistor having an end connected to the ground, and the other end connected to the output of the tri-state buffer. Therefore, it is possible to provide a display control apparatus that is able to perform intermediate color display, with reduced manufacturing cost and reduced power consumption.

Abstract: A closed-caption decoder which uses separate clock generators to produce the sampling frequencies for the clock run-in signal and the data portion of the closed-caption signal. Each of the clock generators generates its signal from a common 12 MHz reference clock signal. The timing of the sampling clock signal for the closed-caption data is advanced at the start of the sampling interval to reduce the total timing errors in the sampling of the closed-caption data. Additionally, the decoder can adaptively select one of four edges of the clock run-in signal to use as its synchronizing reference. Furthermore, the decoder may be adapted to recognize more than one start byte pattern.

Abstract: A data slice circuit is provided for slicing the caption data or the likes included in a television signal at an optimum voltage. A product between a clock-run signal sliced by a comparator at a tentative reference voltage and a clock signal which is 16 times the clock-run signal is stored in a shift register as 16 bit information, and out of them, only the 8 bits around its center are taken in a duty-factor check block, thereby judging the suitability of the slice level. Based on the result obtained, the value of the counter is increased or decreased, and it is taken as a renewed reference voltage through a pulse width conversion circuit and an integration circuit. Also with data sliced by a renewed reference voltage, the check is executed similarly, and a slicing action at an optimum level is achieved.