Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: To ensure the connectability of wiring lines in a semiconductor device having terminals or reservoirs, plural terminals of a cell, which constitutes the semiconductor device, are each formed in a shape having a length corresponding to two or more lattice points. The terminals are arranged so that one or more lattice points are interposed between adjacent terminals. Among the terminals, as to terminals that are adjacent to each other in their shorter direction, it is allowable for them to partially overlap each other in their shorter direction. In this state, second-layer wiring lines are connected to the terminals via through holes, whereby reservoirs can be generated at the terminals, respectively.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: An on-chip multiprocessor having a chip layout for efficient multiprocessor control, wherein multiple processors and shared portions such as shared caches are symmetric with respect to a desired linear axis and a multiprocessor controller is located in the area containing said linear axis. This makes the distances between the processors and the controller equal and shorter, and also decreases differences in the distance between the controller and shared portions, thereby permitting higher speed processing of signals among these.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, a width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line determined in response to a line width of the lines can satisfy a rule and hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: It is intended to ensure the connectability of wiring lines in a semiconductor device having terminals or reservoirs. Plural terminals of a cell which constitutes the semiconductor device are each formed in a shape having a length corresponding to two or more lattice points. The terminals are arranged so that one or more lattice points are interposed between adjacent terminals. Among the terminals, as to the terminals adjacent to each other in their shorter direction, it is allowable for them to partially overlap each other in their shorter direction. In this state, second-layer wiring lines are connected to the terminals via through holes, whereby reservoirs can be generated at the terminals respectively.

Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.

Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.