Patents by Inventor Masayuki Ohuchi

Masayuki Ohuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5049980
    Abstract: Plural semiconductor elements are buried into an insulating substrate, and top surfaces of semiconductor elements and the substrate are in a same plane. A photosensitive dry film is covered on surfaces of the substrate and semiconductor elements. The photosensitive dry film has openings corresponding to electrodes of semiconductor elements, and conductors are filled in openings of the photosensitive dry film. The device has the multi-layer wiring construction without damaging to semiconductor elements arranged on the substrate.
    Type: Grant
    Filed: April 14, 1988
    Date of Patent: September 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tamio Saito, Masayuki Ohuchi, Akira Niitsuma
  • Patent number: 5018051
    Abstract: An IC card is disclosed which comprises a card-shaped main substrate having a surface on which recess portions are formed and an edge portion having a connector layer with an external connector terminal pattern formed thereon, circuit modules embedded in the recess portions in main substrate, each module having electronic components including IC chips, a chip capacitor and a thin D.C. battery unit, and a double-layered wiring structure for providing electric connection between the electronic components and the connector terminal pattern. The double-layered wiring structure comprises a first wiring layer formed on the main substrate to cover the circuit modules and a second wiring layer formed insulatively above the former wiring layer. The first wiring layer has a first wiring pattern that extends in a first direction of the main substrate to be coupled to the electronic components.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: May 21, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Masayuki Ohuchi, Masayuki Saito, Akinori Hongu
  • Patent number: 4997791
    Abstract: An IC card comprises a thermoplastic resin core sheet and an IC chip bearing a conductive projection formed on an electrode of the IC chip, the IC chip being embedded in the core sheet in such a manner that the exposed top surface of the conductive projection is made flush with the main surface of the core sheet. A conductive layer pattern formed on the main surface of the core sheet is extended for contact with the exposed top surface.
    Type: Grant
    Filed: April 13, 1990
    Date of Patent: March 5, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ohuchi, Hirosi Oodaira, Kenichi Yoshida
  • Patent number: 4931853
    Abstract: An IC card comprises a thermoplastic resin core sheet and an IC chip bearing a conductive projection formed on an electrode of the IC chip, the IC chip being embedded in the core sheet in such a manner that the exposed top surface of the conductive projection is made flush with the main surface of the core sheet. A conductive layer pattern formed on the main surface of the core sheet is extended for contact with the exposed top surface.
    Type: Grant
    Filed: September 6, 1989
    Date of Patent: June 5, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ohuchi, Hirosi Oodaira, Kenichi Yoshida
  • Patent number: 4754319
    Abstract: In an IC card according to the present invention, a base sheet formed of thermoplastic material is sandwiched between a substrate sheet and a dummy sheet both formed of nonplastic material lower in thermoplasticity than the base sheet. The substrate sheet is fitted with at least one IC chip and input/output terminals electrically connected to the IC chip. First and second cover sheets formed of thermoplastic material are put individually on the outer surfaces of the substrate sheet and the dummy sheet. The cover sheet on the substrate sheet is formed with apertures through which the input/output terminals are exposed to the outside.
    Type: Grant
    Filed: September 11, 1987
    Date of Patent: June 28, 1988
    Assignees: Kabushiki Kaisha Toshiba, Shoei Printing Company Limited
    Inventors: Tamio Saito, Masayuki Ohuchi, Hirosi Oodaira, Yoshikatsu Fukumoto, Shuji Hiranuma, Ko Kishida, Takanori Kisaka
  • Patent number: 4751126
    Abstract: A circuit board is prepared such that at least two resin substrates are laminated and bonded by thermocompression, a circuit pattern made of a resin composition containing a conductor material is formed on at least one of opposing surfaces of the substrates, a region of the substrate which corresponds to a specific portion of the circuit pattern is recessed, the specific portion of the circuit projects into the recess in accordance with plastic deformation of the substrates and the circuit pattern which is caused by thermocompression bonding, and the specific portion of the circuit pattern constitutes an exposed portion. Multilayer or three-dimensional wiring can be easily achieved in the circuit board.
    Type: Grant
    Filed: July 2, 1986
    Date of Patent: June 14, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirosi Oodaira, Yoshikatsu Fukumoto, Shuji Hiranuma, Masayuki Ohuchi, Tamio Saito
  • Patent number: 4694138
    Abstract: A conductor path is formed by providing an insulating substrate having a surface region which is formed of an insulating composition. The insulating composition contains an organic polymeric material and at least one metal source. The metal source is a metallic powder and/or an organic compound chemically combining a metal or metals. The surface region of the substrate is selectively heated along a predetermined pattern, thereby decomposing and evaporating the organic polymeric material at the heated portion and welding the metal in the heated portion so as to form a conductor path formed of the metal.
    Type: Grant
    Filed: November 30, 1984
    Date of Patent: September 15, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirosi Oodaira, Haruko Suzuki, Masayuki Saito, Masayuki Ohuchi
  • Patent number: 4635356
    Abstract: Terminal-equipped electronic elements, such as chip resistors and chip diodes, are arranged such that one surface of each terminal contacts one surface of a support board, the support board being placed to face a flat plate through a spacer. An electrically insulative liquid synthetic resin is injected between the support board and the flat board and cured to form a synthetic resin layer burying the electronic elements. The support board, flat board and spacer are peeled from the electronic elements and the synthetic resin layer to expose one surface of the terminal of each electronic element on one surface of the synthetic resin layer. A conductive pattern is formed on the synthetic resin layer by screen printing to connect the terminals of the electronic elements.
    Type: Grant
    Filed: August 15, 1985
    Date of Patent: January 13, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ohuchi, Hirosi Oodaira, Kenichi Yoshida