Abstract: A signal processing circuit includes two analog signal processors, an operational amplifier, a rectifier, and a reference potential generator. Each analog signal processor has four input terminals and two output terminals, and is designed to operate such that the first and second output terminals are set at the same potential and that a current difference between the first and second output terminals is proportional to a product of a potential difference between the first and second input terminal and a potential difference between the third and fourth input terminal. The first, second, third and fourth input terminals of the first analog signal processor are connected to receive an input signal, a first reference potential, a second reference potential, and a third reference potential, respectively. The output terminals of the first analog signal processor are connected to the negative and positive input terminals of the operational amplifier, respectively.

Abstract: In an operational amplifier circuit, noise is lowered by using junction FETs as an input transistor pair, and an input operating point and an output operating point can be set at different potentials by connecting a capacitor between an output terminal and an inverting input terminal. For this reason, the operational amplifier circuit can be properly biased and can be operated at a low power supply voltage. In addition, since transistors other than transistors used as constant current sources are constituted by bipolar transistors, the operational amplifier circuit can have wideband frequency characteristics.

Abstract: In the comparator circuit, the amplifier circuit is comprised of an inverting amplifier section having a high gain and a noninverting amplifier section having a low output impedance. Therefore, the comparator circuit has a high input sensitivity. The comparator circuit can also operate at a high speed.

Abstract: In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage.