Patents by Inventor Masayuki Sakakura

Masayuki Sakakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720532
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa
  • Patent number: 10714502
    Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Masayuki Sakakura
  • Publication number: 20200220029
    Abstract: An object is to improve reliability of a light-emitting device. A light-emitting device has a driver circuit portion including a transistor for a driver circuit and a pixel portion including a transistor for a pixel over one substrate. The transistor for the driver circuit and the transistor for the pixel are inverted staggered transistors each including an oxide semiconductor layer in contact with part of an oxide insulating layer. In the pixel portion, a color filter layer and a light-emitting element are provided over the oxide insulating layer. In the transistor for the driver circuit, a conductive layer overlapping with a gate electrode layer and the oxide semiconductor layer is provided over the oxide insulating layer. The gate electrode layer, a source electrode layer, and a drain electrode layer are formed using metal conductive films.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Masayuki SAKAKURA, Yoshiaki OIKAWA, Kenichi OKAZAKI, Hotaka MARUYAMA
  • Publication number: 20200185534
    Abstract: It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinari Higaki, Masayuki Sakakura, Shunpei Yamazaki
  • Publication number: 20200185536
    Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Shunpei Yamazaki, Masayuki Sakakura
  • Patent number: 10679017
    Abstract: To provide an authentication system and a semiconductor device utilizing the system. The semiconductor device includes a transmission/reception circuit, a control circuit, an analog-to-digital converter circuit, a memory device, and a fingerprint sensor. At least one of the control circuit, the analog-to-digital converter circuit, and the memory device includes a transistor including an oxide semiconductor in a channel formation region. The control circuit has a function of receiving an instruction signal from the outside of the semiconductor device through the transmission/reception circuit. The memory device has fingerprint data for comparison and confidential information. The control circuit has a function of comparing fingerprint data to be compared which is obtained by the fingerprint sensor and the fingerprint data for comparison.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: June 9, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Masayuki Sakakura
  • Publication number: 20200176068
    Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Inventors: Masayuki SAKAKURA, Yuugo GOTO, Hiroyuki MIYAKE, Daisuke KUROSAKI
  • Patent number: 10672915
    Abstract: An object is to improve reliability of a light-emitting device. A light-emitting device has a driver circuit portion including a transistor for a driver circuit and a pixel portion including a transistor for a pixel over one substrate. The transistor for the driver circuit and the transistor for the pixel are inverted staggered transistors each including an oxide semiconductor layer in contact with part of an oxide insulating layer. In the pixel portion, a color filter layer and a light-emitting element are provided over the oxide insulating layer. In the transistor for the driver circuit, a conductive layer overlapping with a gate electrode layer and the oxide semiconductor layer is provided over the oxide insulating layer. The gate electrode layer, a source electrode layer, and a drain electrode layer are formed using metal conductive films.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama
  • Publication number: 20200144425
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Application
    Filed: September 3, 2019
    Publication date: May 7, 2020
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Hideomi SUZAWA
  • Patent number: 10629627
    Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transimitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yoshiaki Oikawa, Shunpei Yamazaki, Junichiro Sakata, Masashi Tsubuku, Kengo Akimoto, Miyuki Hosoba
  • Publication number: 20200075635
    Abstract: It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.
    Type: Application
    Filed: November 5, 2019
    Publication date: March 5, 2020
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA
  • Patent number: 10580508
    Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 3, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yuugo Goto, Hiroyuki Miyake, Daisuke Kurosaki
  • Publication number: 20200066761
    Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: Masayuki SAKAKURA, Yoshiaki OIKAWA, Shunpei YAMAZAKI, Junichiro SAKATA, Masashi TSUBUKU, Kengo AKIMOTO, Miyuki HOSOBA
  • Patent number: 10573757
    Abstract: It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinari Higaki, Masayuki Sakakura, Shunpei Yamazaki
  • Publication number: 20200059625
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Motomu KURATA, Hiroyuki HATA, Mitsuhiro ICHIJO, Takashi OHTSUKI, Aya ANZAI, Masayuki SAKAKURA
  • Patent number: 10566460
    Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura
  • Publication number: 20200035708
    Abstract: An object of the present invention is to decrease substantial resistance of art electrode such as a transparent electrode or a wiring, and furthermore, to provide a display device for which is possible to apply same voltage to light-emitting elements. In the invention, a auxiliary wiring that is formed in one layer in which a conductive, film of a semiconductor element such as an electrode, wiring, a signal line, a scanning line, or a power supply line is connected to an electrode typified by a second electrode, and a wiring. It is preferable that the auxiliary wiring is formed into a conductive film to include low resistive material, especially, formed to include lower resistive, material than the resistance of an electrode and a wiring that is required to reduce the resistance.
    Type: Application
    Filed: August 7, 2019
    Publication date: January 30, 2020
    Inventors: Noriko Miyagi, Masayuki Sakakura, Tatsuya Arao, Ritsuko Nagao, Yoshifumi Tanada
  • Publication number: 20200020835
    Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 16, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru TSUCHIYA, Aya ANZAI, Masayuki SAKAKURA, Masaharu NAGAI, Yutaka MATSUDA
  • Patent number: 10522568
    Abstract: It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura
  • Patent number: 10516010
    Abstract: The light-emitting apparatus comprising thin film transistors and light emitting elements, comprises; a second inorganic insulation layer on a gate electrode, a first organic insulation layer on the second inorganic insulation layer, a third inorganic insulation layer on the first organic insulation layer, an anode on the third inorganic insulation layer, a second organic insulation layer overlapping with the end of the anode and having an inclination angle of 35 to 45 degrees, a fourth inorganic insulation layer on the upper and side surfaces of the second organic insulation layer and having an opening over the anode, an organic compound layer in contact with the anode and the fourth inorganic insulation layer and containing light-emitting material, and a cathode in contact with the organic compound layer, wherein the third and the fourth inorganic insulation layers comprise silicon nitride or aluminum nitride.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: December 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masayuki Sakakura, Toru Takayama